JPS5917090U - data transfer system - Google Patents

data transfer system

Info

Publication number
JPS5917090U
JPS5917090U JP11310082U JP11310082U JPS5917090U JP S5917090 U JPS5917090 U JP S5917090U JP 11310082 U JP11310082 U JP 11310082U JP 11310082 U JP11310082 U JP 11310082U JP S5917090 U JPS5917090 U JP S5917090U
Authority
JP
Japan
Prior art keywords
data
data transfer
transfer system
stored
storage device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11310082U
Other languages
Japanese (ja)
Inventor
金子　由雄
Original Assignee
横河電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 横河電機株式会社 filed Critical 横河電機株式会社
Priority to JP11310082U priority Critical patent/JPS5917090U/en
Publication of JPS5917090U publication Critical patent/JPS5917090U/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案に係るシステム例を示すブロック図、第
２図は本考案で用いる低速記憶装置部Ｓの要部の具体例
を示すブロック図である。 Ｆ・・・高速記憶装置部、Ｓ・・・低速記憶装置部、Ｃ
・・・処理装置部、Ｌｌ・・・データバス、Ｌ２・・・
制御線、５ＥＬＩ、２・・・セレクタ、ＢＭＩ、８Ｍ２
・・・バッファメモリ、ＣＴＬ・・・制御部、ＭＴ・・
・磁気テープ装置、ＥＲＲＩ、ＥＲＲ２・・・エラー検
出回路。FIG. 1 is a block diagram showing an example of a system according to the present invention, and FIG. 2 is a block diagram showing a specific example of a main part of a low-speed storage unit S used in the present invention. F...High speed storage unit, S...Low speed storage unit, C
...Processing device section, Ll...Data bus, L2...
Control line, 5ELI, 2...Selector, BMI, 8M2
...Buffer memory, CTL...Control unit, MT...
・Magnetic tape device, ERRI, ERR2...Error detection circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] データ転送速度が異なる記憶装置間でデータ転送を行う
ように構成されたデータ転送システムにおいて、格納さ
れた全データが転送されることにより各記憶装置との接
続が相補的に切り換えられる２個のバッファメモリを低
速記憶装置部に設け、一方のバッファメモリに一方の記
憶装置から転送′　されるデータを格納しながら他方の
バッファメモリに格納されたデータを他方の記憶装置に
転送することを特徴とするデータ転送システム。In a data transfer system configured to transfer data between storage devices with different data transfer speeds, two buffers are used to switch connections with each storage device in a complementary manner by transferring all stored data. A memory is provided in the low-speed storage unit, and data transferred from one storage device is stored in one buffer memory while data stored in the other buffer memory is transferred to the other storage device. Data transfer system.
JP11310082U 1982-07-26 1982-07-26 data transfer system Pending JPS5917090U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11310082U JPS5917090U (en) 1982-07-26 1982-07-26 data transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11310082U JPS5917090U (en) 1982-07-26 1982-07-26 data transfer system

Publications (1)

Publication Number Publication Date
JPS5917090U true JPS5917090U (en) 1984-02-01

Family

ID=30261938

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11310082U Pending JPS5917090U (en) 1982-07-26 1982-07-26 data transfer system

Country Status (1)

Country Link
JP (1) JPS5917090U (en)

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