JPS5810299U - Memory addressing device for parallel processing - Google Patents

Memory addressing device for parallel processing

Info

Publication number
JPS5810299U
JPS5810299U JP10396481U JP10396481U JPS5810299U JP S5810299 U JPS5810299 U JP S5810299U JP 10396481 U JP10396481 U JP 10396481U JP 10396481 U JP10396481 U JP 10396481U JP S5810299 U JPS5810299 U JP S5810299U
Authority
JP
Japan
Prior art keywords
parallel processing
address
memory
memory addressing
addressing device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10396481U
Other languages
Japanese (ja)
Inventor
志村　栄政
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP10396481U priority Critical patent/JPS5810299U/en
Publication of JPS5810299U publication Critical patent/JPS5810299U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、従来の並列処理におけるメモリー系統図、第
２図は、本考案の並列処理のメモリー系統図である。 １・・・外部記憶装置、２・・・メモリー、３．５・・
・アドレスレジスタ、６・・・処理装置、７・・・コン
トローラ、８．９・・・切換器、１０・・・インバータ
。FIG. 1 is a memory system diagram for conventional parallel processing, and FIG. 2 is a memory system diagram for parallel processing according to the present invention. 1...External storage device, 2...Memory, 3.5...
- Address register, 6... Processing device, 7... Controller, 8.9... Switch, 10... Inverter.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 高速並列処理に使用するバッファメモリーを１個のメモ
リーと２個のアドレスレジスタで構成し、アドレスレジ
スタ１を０番地方向から他の一方のアドレスレジスタを
アドレスＦＵＬＬ方向より指定するよう構成してこの２
個のアドレスレジスタの出力を切換えることにより１個
のメモリーで、２バツクを使用したメモリーと同等のバ
ッファメモリーを構成できる並列処理用メモリーのアド
レス・装置。The buffer memory used for high-speed parallel processing is composed of one memory and two address registers, and address register 1 is configured to be specified from the 0 address direction to the other address register from the address FULL direction.
A memory address device for parallel processing that can configure a buffer memory equivalent to a memory using two buffers with one memory by switching the outputs of two address registers.
JP10396481U 1981-07-15 1981-07-15 Memory addressing device for parallel processing Pending JPS5810299U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10396481U JPS5810299U (en) 1981-07-15 1981-07-15 Memory addressing device for parallel processing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10396481U JPS5810299U (en) 1981-07-15 1981-07-15 Memory addressing device for parallel processing

Publications (1)

Publication Number Publication Date
JPS5810299U true JPS5810299U (en) 1983-01-22

Family

ID=29898570

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10396481U Pending JPS5810299U (en) 1981-07-15 1981-07-15 Memory addressing device for parallel processing

Country Status (1)

Country Link
JP (1) JPS5810299U (en)

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