JPS58187833U - data transfer circuit - Google Patents
data transfer circuitInfo
- Publication number
- JPS58187833U JPS58187833U JP8585182U JP8585182U JPS58187833U JP S58187833 U JPS58187833 U JP S58187833U JP 8585182 U JP8585182 U JP 8585182U JP 8585182 U JP8585182 U JP 8585182U JP S58187833 U JPS58187833 U JP S58187833U
- Authority
- JP
- Japan
- Prior art keywords
- data
- memories
- sets
- computer
- data transfer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案に係るデータ転送回路の１例とその周辺
回路を描いた図、第２図はメモリＭ□とＭ２が時間とと
もにどのように動作しているかを示す図である。
Ａ□〜Ａ８・・・バッファ、Ｍ１９Ｍ２・・・メモリ、
Ｂ・・・転送カウンタ、Ｃ・・・ゼロ検出器、Ｇ・・・
ゲート、ＦＦ・・・フリップフロップ。FIG. 1 is a diagram depicting an example of a data transfer circuit according to the present invention and its peripheral circuits, and FIG. 2 is a diagram showing how memories M□ and M2 operate over time. A□~A8...Buffer, M19M2...Memory,
B... Transfer counter, C... Zero detector, G...
Gate, FF...flip flop.
Claims (1)
おいて、 コンピュータとＩ１０間に転送するデータの数をコンピ
ュータ゛からの指令により設定しデータの転送ごとにこ
れをカウントする転送カウンタと、複数のデータを格納
できる２組のメモリと、この２組のメモリの入出力信号
を開閉するバッファと、このバッファを制御するフリッ
プフロップとを備え、 一方のメモリへコンピュータからのデータを書き込んで
いる期間、他方のメモリからはデータをＩｌｏへ転送で
きるようにし、この２組のメモリを交互に使い分けるよ
うに前記フリップフロップでバッファの側御を行なうよ
うにしたデータ転送回路。[Claims for Utility Model Registration] A transfer counter that sets the number of data to be transferred between the computer and the I10 according to a command from the computer and counts this number each time data is transferred, in a circuit intervening in data transfer between the computer and the I10. It is equipped with two sets of memories that can store multiple data, a buffer that opens and closes the input/output signals of these two sets of memories, and a flip-flop that controls these buffers.Data from the computer is written to one of the memories. The data transfer circuit is configured to allow data to be transferred from the other memory to Ilo during a period of time, and to control the buffer by the flip-flop so that the two sets of memories are used alternately.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8585182U JPS58187833U (en) | 1982-06-09 | 1982-06-09 | data transfer circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8585182U JPS58187833U (en) | 1982-06-09 | 1982-06-09 | data transfer circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58187833U true JPS58187833U (en) | 1983-12-13 |
Family
ID=30094693
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8585182U Pending JPS58187833U (en) | 1982-06-09 | 1982-06-09 | data transfer circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58187833U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5389634A (en) * | 1977-01-19 | 1978-08-07 | Nec Corp | Data transfer system |
| JPS55134442A (en) * | 1979-04-04 | 1980-10-20 | Hitachi Ltd | Data transfer unit |
-
1982
- 1982-06-09 JP JP8585182U patent/JPS58187833U/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5389634A (en) * | 1977-01-19 | 1978-08-07 | Nec Corp | Data transfer system |
| JPS55134442A (en) * | 1979-04-04 | 1980-10-20 | Hitachi Ltd | Data transfer unit |
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