JPS60144332U - Serial data input - parallel data output circuit - Google Patents
Serial data input - parallel data output circuitInfo
- Publication number
- JPS60144332U JPS60144332U JP3158884U JP3158884U JPS60144332U JP S60144332 U JPS60144332 U JP S60144332U JP 3158884 U JP3158884 U JP 3158884U JP 3158884 U JP3158884 U JP 3158884U JP S60144332 U JPS60144332 U JP S60144332U
- Authority
- JP
- Japan
- Prior art keywords
- data
- shift register
- data output
- input
- output circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Information Transfer Systems (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は本考案によるシリアルデータ入力−パラレルデ
ータ出力回路の一実施例を示す回路図、第2図は第1図
の動作説明に供するタイムチャートである。
SR1〜SR8・・・シフトレジスタ、SRG・・・シ
フトレジスタ群、PSCNT・・・プリセットカウンタ
ー、DCR・・・デコーダ。FIG. 1 is a circuit diagram showing an embodiment of the serial data input/parallel data output circuit according to the present invention, and FIG. 2 is a time chart for explaining the operation of FIG. 1. SR1 to SR8...shift register, SRG...shift register group, PSCNT...preset counter, DCR...decoder.
Claims (1)
力されるシリアルデータを所定のビット要分連続して保
持するためにカスケード接続したシフトレジスタ群と、
任意のカウントデータがプリセットできかつデータリー
ド信号の入力によりカウントデータを順次1づつ更新す
るプリセットカウンターi、このプリセットカウンター
のカウントデータに対応して前記シフトレジスタ群の特
゛定のシフトレジスタに対してパラレルデータの出力要
求信号を生成するデコーダとにより構成され、所定のビ
ット要分連続して入力されたシリアルデ二りをシフトレ
ジスタ単位に任意のビット列を指定して読出し得るよう
にしたことを特徴とするシリアルデータ入力−パラレル
データ出力回路。a shift register group in which shift registers having a parallel data output function are cascaded to continuously hold a predetermined number of bits of input serial data;
A preset counter i that can be preset with arbitrary count data and that sequentially updates the count data by 1 by inputting a data read signal, and a preset counter i that can sequentially update the count data by 1 by inputting a data read signal, and a preset counter i that corresponds to the count data of this preset counter to a specific shift register of the shift register group. and a decoder that generates a parallel data output request signal, and is characterized in that serial digital data continuously input for a predetermined number of bits can be read out by specifying an arbitrary bit string for each shift register. Serial data input-parallel data output circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3158884U JPS60144332U (en) | 1984-03-07 | 1984-03-07 | Serial data input - parallel data output circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3158884U JPS60144332U (en) | 1984-03-07 | 1984-03-07 | Serial data input - parallel data output circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60144332U true JPS60144332U (en) | 1985-09-25 |
Family
ID=30532320
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3158884U Pending JPS60144332U (en) | 1984-03-07 | 1984-03-07 | Serial data input - parallel data output circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60144332U (en) |
-
1984
- 1984-03-07 JP JP3158884U patent/JPS60144332U/en active Pending
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