JPS5933551U - data reading device - Google Patents

data reading device

Info

Publication number
JPS5933551U
JPS5933551U JP1982129153U JP12915382U JPS5933551U JP S5933551 U JPS5933551 U JP S5933551U JP 1982129153 U JP1982129153 U JP 1982129153U JP 12915382 U JP12915382 U JP 12915382U JP S5933551 U JPS5933551 U JP S5933551U
Authority
JP
Japan
Prior art keywords
reading device
data reading
data
shift register
latch circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1982129153U
Other languages
Japanese (ja)
Inventor
淳 中山
松本　繁雄
一豊 関根
Original Assignee
ソニー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ソニー株式会社 filed Critical ソニー株式会社
Priority to JP1982129153U priority Critical patent/JPS5933551U/en
Publication of JPS5933551U publication Critical patent/JPS5933551U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来例を示す回路ブロック図、第２図は本考案
の実施例を孝子回路ブロック図、第３図はデータ処理方
法を説明するための図である。 なお図面に用いられている符号において、１・・・マイ
クロプロセッサ、４・・・ＲＡＭ、１０・・・ｍビット
シフトレジスタ、１２・・・ｍビットラッチ回路、であ
る。FIG. 1 is a circuit block diagram showing a conventional example, FIG. 2 is a circuit block diagram showing an embodiment of the present invention, and FIG. 3 is a diagram for explaining a data processing method. In the symbols used in the drawings, 1...microprocessor, 4...RAM, 10...m-bit shift register, 12...m-bit latch circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ｎビットシリアルデータが入力されｍ（ｍ（ｎ）ビット
パラレルデータが出力されるように成されたシフトレジ
スタと、このシフトレジスタから出力される上記ｍビッ
トパラレルデータが格納されるラッチ回路と、このラッ
チ回路の出力が供給されるワンチップマイクロプロセッ
サとから成るデータ読取り装置。A shift register configured to input n-bit serial data and output m (m(n)-bit parallel data); a latch circuit in which the m-bit parallel data outputted from the shift register is stored; A data reading device consisting of a one-chip microprocessor to which the output of a latch circuit is supplied.
JP1982129153U 1982-08-26 1982-08-26 data reading device Pending JPS5933551U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982129153U JPS5933551U (en) 1982-08-26 1982-08-26 data reading device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982129153U JPS5933551U (en) 1982-08-26 1982-08-26 data reading device

Publications (1)

Publication Number Publication Date
JPS5933551U true JPS5933551U (en) 1984-03-01

Family

ID=30292733

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982129153U Pending JPS5933551U (en) 1982-08-26 1982-08-26 data reading device

Country Status (1)

Country Link
JP (1) JPS5933551U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05237716A (en) * 1992-08-11 1993-09-17 Mitsubishi Materials Corp Cutter fastening mechanism

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05237716A (en) * 1992-08-11 1993-09-17 Mitsubishi Materials Corp Cutter fastening mechanism

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