JPS59187495U - figure drawing circuit - Google Patents
figure drawing circuitInfo
- Publication number
- JPS59187495U JPS59187495U JP8112383U JP8112383U JPS59187495U JP S59187495 U JPS59187495 U JP S59187495U JP 8112383 U JP8112383 U JP 8112383U JP 8112383 U JP8112383 U JP 8112383U JP S59187495 U JPS59187495 U JP S59187495U
- Authority
- JP
- Japan
- Prior art keywords
- shift register
- flip
- circuit
- output
- flop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Record Information Processing For Printing (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は点列データで作画を行う例を示す図、第２図は
作画系の信号変換を示すブロック図、第３図はシリアル
データに転送する回路例を示す図、第４図は従来のシフ
トレジスタ部の回路図、第５図は本考案によるシフトレ
ジスタ部の一実施例を示す回路図である。
１・・・・・・用紙、２・・・・・・作中図、３・・曲
複製図、４゜２４・・・・・・作画機器、２１・・・・
・・ベクタデータ、２２・・・・・・ラスタデータ変換
、２３・・・・・・シリアルデータ変換、３１・・・・
・・演算回路、３２・・・・・・メモリ、３３ ′−１
〜３３〜ｎ・・・・・・メモリＲ１３４−−−−−−シ
フトレジスタ、４１．４１−１〜４１−ｍ・・・・・・
Ｄ形フリップフロップ素子、５１・・・・・・ＯＲ素子
、５２・・・・・・ＡＮＤ素子。Figure 1 is a diagram showing an example of drawing using point sequence data, Figure 2 is a block diagram showing signal conversion in the drawing system, Figure 3 is a diagram showing an example of a circuit that transfers to serial data, and Figure 4 is a conventional example. FIG. 5 is a circuit diagram showing an embodiment of the shift register section according to the present invention. 1...paper, 2...drawing drawings, 3...music reproduction drawings, 4゜24...drawing equipment, 21...
...Vector data, 22... Raster data conversion, 23... Serial data conversion, 31...
...Arithmetic circuit, 32...Memory, 33'-1
~33~n...Memory R134-----Shift register, 41.41-1~41-m...
D-type flip-flop element, 51...OR element, 52...AND element.
Claims (1)
ンの点列データを順次時系列でフリップフロップ素子群
より構成されるシフトレジスタ、該シフトレジスタによ
り転送を行う回路で前記フリップフロップ素子群の少な
くとも１・個所を接続する場合に、前記シフトレジスタ
出力と制御信号との論理積、該論理積出力と前段のフリ
ップフロップ素子出力との論理和を、次段のフリップフ
ロップ素子の入力とする接続を行う回路を有して成るこ
とを特徴とする図形作画回路。In a device that draws figures using point sequence data, a shift register is constructed of a group of flip-flop elements in which one line of point sequence data is sequentially transferred in time series, and a circuit that transfers data using the shift register includes at least one of the flip-flop element groups. - When connecting points, connect the logical product of the shift register output and the control signal, and the logical sum of the logical product output and the previous stage flip-flop element output as input to the next stage flip-flop element. A graphic drawing circuit comprising a circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8112383U JPS59187495U (en) | 1983-05-31 | 1983-05-31 | figure drawing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8112383U JPS59187495U (en) | 1983-05-31 | 1983-05-31 | figure drawing circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59187495U true JPS59187495U (en) | 1984-12-12 |
| JPH051437Y2 JPH051437Y2 (en) | 1993-01-14 |
Family
ID=30211094
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8112383U Granted JPS59187495U (en) | 1983-05-31 | 1983-05-31 | figure drawing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59187495U (en) |
-
1983
- 1983-05-31 JP JP8112383U patent/JPS59187495U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH051437Y2 (en) | 1993-01-14 |
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