JPS5939499U - Main memory error bit display circuit - Google Patents
Main memory error bit display circuitInfo
- Publication number
- JPS5939499U JPS5939499U JP13131082U JP13131082U JPS5939499U JP S5939499 U JPS5939499 U JP S5939499U JP 13131082 U JP13131082 U JP 13131082U JP 13131082 U JP13131082 U JP 13131082U JP S5939499 U JPS5939499 U JP S5939499U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- error bit
- display circuit
- main memory
- memory error
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Debugging And Monitoring (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のエラーピット表示回路を示すブロック図
、第２図は本考案の一実施例を示すブロック図、第３図
は第２図の動作タイミング図である。
３ ：ＥＣＣ回路、７ａＨラッチ回路、１２：表示回路
、１３：フリップフロップ。FIG. 1 is a block diagram showing a conventional error pit display circuit, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is an operation timing chart of FIG. 3: ECC circuit, 7aH latch circuit, 12: Display circuit, 13: Flip-flop.
Claims (1)
うＥＣＣ回路と、このＥＣＣ回路から出力されるエラー
発生信号出力によりセットされるフリップフロップと、
このフリップフロップの出力信号をラッチクロックとし
て上記ＥＣＣ回路から出力されるエラービットデータを
保持するラッチ回路と、このラッチ回路のエラービット
データ表示する表示回路とを具備することを特徴とする
主記憶装置のエラービット表示回路。an ECC circuit that performs bit correction each time a single bit error occurs; a flip-flop that is set by an error occurrence signal output from the ECC circuit;
A main memory device comprising: a latch circuit that uses the output signal of the flip-flop as a latch clock to hold error bit data output from the ECC circuit; and a display circuit that displays the error bit data of the latch circuit. error bit display circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13131082U JPS5939499U (en) | 1982-09-01 | 1982-09-01 | Main memory error bit display circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13131082U JPS5939499U (en) | 1982-09-01 | 1982-09-01 | Main memory error bit display circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5939499U true JPS5939499U (en) | 1984-03-13 |
Family
ID=30296905
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13131082U Pending JPS5939499U (en) | 1982-09-01 | 1982-09-01 | Main memory error bit display circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5939499U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60190767U (en) * | 1984-05-24 | 1985-12-17 | 日本電気株式会社 | Feeding device for mail, etc. |
-
1982
- 1982-09-01 JP JP13131082U patent/JPS5939499U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60190767U (en) * | 1984-05-24 | 1985-12-17 | 日本電気株式会社 | Feeding device for mail, etc. |
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