JPS61168761U - - Google Patents

Info

Publication number
JPS61168761U
JPS61168761U JP5128885U JP5128885U JPS61168761U JP S61168761 U JPS61168761 U JP S61168761U JP 5128885 U JP5128885 U JP 5128885U JP 5128885 U JP5128885 U JP 5128885U JP S61168761 U JPS61168761 U JP S61168761U
Authority
JP
Japan
Prior art keywords
image data
mask data
ram
address
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5128885U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5128885U priority Critical patent/JPS61168761U/ja
Publication of JPS61168761U publication Critical patent/JPS61168761U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Image Processing (AREA)
  • Editing Of Facsimile Originals (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案による画像入力装置を示すブロ
ツク回路図、第２図は第１図の説明に使用する波
形図である。 １：カウンタ、２：ＣＰＵ、３：データセレク
タ、４：出力ポート、５：ＲＡＭ、６：フリツプ
フロツプ、７：アンド回路、８：フリツプフロツ
プ、９：アドレスバス、１０：データバス、ｔ１
〜ｔ５：端子。 FIG. 1 is a block circuit diagram showing an image input device according to the present invention, and FIG. 2 is a waveform diagram used to explain FIG. 1. 1: Counter, 2: CPU, 3: Data selector, 4: Output port, 5: RAM, 6: Flip-flop, 7: AND circuit, 8: Flip-flop, 9: Address bus, 10: Data bus, t1
~t5: Terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 縮小率に対応したマスクデータが記憶されたＲ
ＡＭと、このＲＡＭに対するアドレス信号を順次
発生させるアドレス手段と、上記アドレス信号に
基づき上記ＲＡＭから上記マスクデータを順次読
み出す手段と、上記記憶手段から読み出された上
記マスクデータと縮小すべき画像データとの論理
積をとることにより画像データをマスクする手段
とを備えた画像入力装置。 R in which mask data corresponding to the reduction ratio is stored
AM, address means for sequentially generating address signals for the RAM, means for sequentially reading out the mask data from the RAM based on the address signal, and the mask data read from the storage means and the image data to be reduced. an image input device comprising means for masking image data by performing a logical AND with the image data.
JP5128885U 1985-04-05 1985-04-05 Pending JPS61168761U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5128885U JPS61168761U (en) 1985-04-05 1985-04-05

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5128885U JPS61168761U (en) 1985-04-05 1985-04-05

Publications (1)

Publication Number Publication Date
JPS61168761U true JPS61168761U (en) 1986-10-20

Family

ID=30570193

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5128885U Pending JPS61168761U (en) 1985-04-05 1985-04-05

Country Status (1)

Country Link
JP (1) JPS61168761U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01314329A (en) * 1988-06-14 1989-12-19 Fujitsu Ltd Image data processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01314329A (en) * 1988-06-14 1989-12-19 Fujitsu Ltd Image data processor

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