JPS5990995U - display device - Google Patents

display device

Info

Publication number
JPS5990995U
JPS5990995U JP18687882U JP18687882U JPS5990995U JP S5990995 U JPS5990995 U JP S5990995U JP 18687882 U JP18687882 U JP 18687882U JP 18687882 U JP18687882 U JP 18687882U JP S5990995 U JPS5990995 U JP S5990995U
Authority
JP
Japan
Prior art keywords
address
memory
display device
information stored
converter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18687882U
Other languages
Japanese (ja)
Inventor
努 伊藤
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP18687882U priority Critical patent/JPS5990995U/en
Publication of JPS5990995U publication Critical patent/JPS5990995U/en
Pending legal-status Critical Current

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  • Digital Computer Display Output (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本考案の実施例構成図である。 CPtJ、ホストコンピュータ、W:書込回路、Bニス
クリーンバッファAvJ:書込アドレス発生部、AT:
書込アドレス変換部、S:並直変換部。
The drawing is a configuration diagram of an embodiment of the present invention. CPtJ, host computer, W: write circuit, B second screen buffer AvJ: write address generator, AT:
Write address converter, S: Parallel-to-serial converter.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ホストコンピュータ側に設けた第1のメモリに格納され
ているパターン情報を畜える第2のメモリを有し、該第
2のメモリに畜えられたパターン情報に基いて、パター
ン表示を行う表示装置において、前記第1のメモリのア
ドレスを変換して前記第2のメモリのアドレスとするア
ドレス変換部を設け、該アドレス変換部から出力される
アドレス信号により指定されるアドレスを前記第2のメ
モリの書込アドレスとすることを特徴とする表示装置。
A display device that has a second memory that stores pattern information stored in a first memory provided on the host computer side, and displays a pattern based on the pattern information stored in the second memory. An address converter is provided to convert the address of the first memory into an address of the second memory, and the address specified by the address signal output from the address converter is converted to the address of the second memory. A display device characterized by a write address.
JP18687882U 1982-12-10 1982-12-10 display device Pending JPS5990995U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18687882U JPS5990995U (en) 1982-12-10 1982-12-10 display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18687882U JPS5990995U (en) 1982-12-10 1982-12-10 display device

Publications (1)

Publication Number Publication Date
JPS5990995U true JPS5990995U (en) 1984-06-20

Family

ID=30403531

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18687882U Pending JPS5990995U (en) 1982-12-10 1982-12-10 display device

Country Status (1)

Country Link
JP (1) JPS5990995U (en)

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