JPS6020651U - Image display control device - Google Patents
Image display control deviceInfo
- Publication number
- JPS6020651U JPS6020651U JP11156783U JP11156783U JPS6020651U JP S6020651 U JPS6020651 U JP S6020651U JP 11156783 U JP11156783 U JP 11156783U JP 11156783 U JP11156783 U JP 11156783U JP S6020651 U JPS6020651 U JP S6020651U
- Authority
- JP
- Japan
- Prior art keywords
- write
- address
- display
- display memory
- control device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Digital Computer Display Output (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の画像表示制御装置の回路構成を示すブロ
ック図、第２図は本考案の一実施例に係る画像表示装置
の回路構成を示すブロック図である。
２１．２３・・・読み出しアドレス発生回路、２２゜２
４・・・表示装置、２５．２６・・・アドレス切換回路
、２７・・・書き込みアドレス発生回路、２８．３３・
・・接続バス、２９．３０・・・表示用メモリ。FIG. 1 is a block diagram showing the circuit configuration of a conventional image display control device, and FIG. 2 is a block diagram showing the circuit configuration of an image display device according to an embodiment of the present invention. 21.23...Read address generation circuit, 22゜2
4...Display device, 25.26...Address switching circuit, 27...Write address generation circuit, 28.33.
...Connection bus, 29.30...Display memory.
Claims (1)
めの第１、第２表示用メモリと、書き込みアドレスを発
生する書き込みアドレス発生回路と、各表示用メモリへ
の読み出しアドレスを発生する第１、第２読み出しアド
レス発生回路と、各表示メモリへのアドレスを書き込み
及び読み出し動作のタイミングに合わせてそれぞれ切り
換える第１、第２アドレス切換回路とを具備し、送られ
て来る画像データの導出バスを前記第１表示用メモリに
接続し、この第１表示用メモリに前記画像データを書き
込むべく前記書き込みアドレス発生回路の出力バスを前
記第１アドレス切換回路の書き込みアドレス取り込み側
に接続し、前記第１表示用メモリのデータ出力バスを前
記第２表示用メモリの書き込み入力側にも接続し、かつ
、前記第１アドレス発生回路の出力バスを前記第２アド
レス切換回路の書き込みアドレス取り込み側にも接続し
て成る画像表示制御装置。At least two first and second display devices, first and second display memories for each display device, a write address generation circuit that generates a write address, and a read address for each display memory. and first and second address switching circuits that switch addresses to each display memory in accordance with the timing of write and read operations. connecting a derivation bus to the first display memory, and connecting an output bus of the write address generation circuit to the write address capture side of the first address switching circuit in order to write the image data to the first display memory; The data output bus of the first display memory is also connected to the write input side of the second display memory, and the output bus of the first address generation circuit is connected to the write address input side of the second address switching circuit. An image display control device that is connected to
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11156783U JPS6020651U (en) | 1983-07-20 | 1983-07-20 | Image display control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11156783U JPS6020651U (en) | 1983-07-20 | 1983-07-20 | Image display control device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6020651U true JPS6020651U (en) | 1985-02-13 |
Family
ID=30258987
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11156783U Pending JPS6020651U (en) | 1983-07-20 | 1983-07-20 | Image display control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6020651U (en) |
-
1983
- 1983-07-20 JP JP11156783U patent/JPS6020651U/en active Pending
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