JPS6047058U - channel control device - Google Patents
channel control deviceInfo
- Publication number
- JPS6047058U JPS6047058U JP12306284U JP12306284U JPS6047058U JP S6047058 U JPS6047058 U JP S6047058U JP 12306284 U JP12306284 U JP 12306284U JP 12306284 U JP12306284 U JP 12306284U JP S6047058 U JPS6047058 U JP S6047058U
- Authority
- JP
- Japan
- Prior art keywords
- command
- storage area
- processing unit
- main processing
- main memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案に係るチャネル制御システムの一実施例
、第２図は本考案の一実施である。
図において１は主処理装置、２は主記憶メモリ、３は共
通バス、４はバスコントロール回路、５はチャネル装置
、６はＤＭＡ制御回路、７はコマンドレジスタ、８はス
テータスレジスタ、９は割込み制御ビット格納エリア、
・１０はローカルバス、１１乃至１１″はサブチャネル
装置、１２はターミナル、１３はサブ処理装置、１４は
共通バス、１５はサブ記憶メモリをそれぞれ示す。FIG. 1 shows an embodiment of a channel control system according to the present invention, and FIG. 2 shows an implementation of the present invention. In the figure, 1 is the main processing unit, 2 is the main memory, 3 is the common bus, 4 is the bus control circuit, 5 is the channel device, 6 is the DMA control circuit, 7 is the command register, 8 is the status register, and 9 is the interrupt control bit storage area,
10 is a local bus, 11 to 11'' are sub-channel devices, 12 is a terminal, 13 is a sub-processing device, 14 is a common bus, and 15 is a sub-storage memory.
Claims (1)
るチャネル装置、該共通バスに接続され主処理装置及び
チャネル装置よりＤＭＡ制御により記憶／読出しが行な
われる主記憶メモリ、チャネル装置上に設けられ共通バ
スを介して主処理装置によるアクセスが可能なインタフ
ェースレジスタを備え、主処理装置よりインタフェース
レジスタ上にコマンドをセットしてチャンネル装置を起
動スるシステムにおいて、 前記インタフェースレジスタに、コマンド格納領域と、
このコマンド格納領域に格納される情報がコマンドであ
るかコマンドが格納される主記憶メモリ上のアドレス情
報であるかを表示する割込ビット格納エリアとを設ける
とともに、チャネル装置へ送出するコマンドの長さに応
じて当該コマンドを前記インタフェースレジスタのコマ
ンド格納領域にセットするか主記憶メモリにセットする
かを判断し、該コマンドを主記憶メモリにセットする場
合はセットした主記憶メモリのアドレスをインタフェー
スレジスタのコマンド格納領域にセットし、且つ前記割
込ビット格納エリアにその旨を示すビット情報をセット
する制御手段を前記主処理装置に設けたことを特徴どす
るチャネル制御装置。[Claims for Utility Model Registration] A main processing unit, a channel device connected to the main processing unit via a common bus, and storage/reading performed by the main processing unit and the channel device connected to the common bus under DMA control. In a system comprising a main memory and an interface register provided on the channel device and accessible by the main processing unit via a common bus, the main processing unit sets a command on the interface register to start the channel device, The interface register includes a command storage area, and
An interrupt bit storage area is provided to display whether the information stored in this command storage area is a command or address information on the main memory where the command is stored, and the length of the command sent to the channel device. Depending on the command, it is determined whether to set the command in the command storage area of the interface register or in the main memory, and if the command is to be set in the main memory, the address of the set main memory is stored in the interface register. 2. A channel control device characterized in that said main processing device is provided with control means for setting a command storage area in said interrupt bit storage area, and setting bit information indicating this in said interrupt bit storage area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12306284U JPS6047058U (en) | 1984-08-11 | 1984-08-11 | channel control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12306284U JPS6047058U (en) | 1984-08-11 | 1984-08-11 | channel control device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6047058U true JPS6047058U (en) | 1985-04-02 |
Family
ID=30281057
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12306284U Pending JPS6047058U (en) | 1984-08-11 | 1984-08-11 | channel control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6047058U (en) |
-
1984
- 1984-08-11 JP JP12306284U patent/JPS6047058U/en active Pending
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