JPS59187850U - memory circuit addressing device - Google Patents

memory circuit addressing device

Info

Publication number
JPS59187850U
JPS59187850U JP8019283U JP8019283U JPS59187850U JP S59187850 U JPS59187850 U JP S59187850U JP 8019283 U JP8019283 U JP 8019283U JP 8019283 U JP8019283 U JP 8019283U JP S59187850 U JPS59187850 U JP S59187850U
Authority
JP
Japan
Prior art keywords
memory circuit
addressing device
circuit addressing
accessed
normally
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8019283U
Other languages
Japanese (ja)
Inventor
秀和 金子
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP8019283U priority Critical patent/JPS59187850U/en
Publication of JPS59187850U publication Critical patent/JPS59187850U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図は、本考案の一実施例を示す概略図である。 １・・・データ処理回路、２・・・記憶回路、３・・・
アドレス変換回路、４・・・付加記憶回路、５．６・・
・データバス、７．８・・・アドレスバス、９・・・ア
ドレス変換制御信号。The figure is a schematic diagram showing an embodiment of the present invention. 1... Data processing circuit, 2... Memory circuit, 3...
Address conversion circuit, 4... Additional storage circuit, 5.6...
- Data bus, 7.8...Address bus, 9...Address conversion control signal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 記憶回路のあるアドレスにおいてのみ、通常処理するデ
ータ長より長いビットを有するデータを処理することが
ある処理装置の記憶回路において、記憶回路を通常アク
セスする時間と同一の時間でアクセス可能で、又、記憶
回路の未使用の領域を実装不用とすることを特徴とする
記憶回路アドレス装置。In a memory circuit of a processing device that may process data having a bit longer than the data length normally processed only at a certain address of the memory circuit, the memory circuit can be accessed in the same time as the time when the memory circuit is normally accessed, and A memory circuit addressing device characterized in that an unused area of a memory circuit is not required for mounting.
JP8019283U 1983-05-30 1983-05-30 memory circuit addressing device Pending JPS59187850U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8019283U JPS59187850U (en) 1983-05-30 1983-05-30 memory circuit addressing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8019283U JPS59187850U (en) 1983-05-30 1983-05-30 memory circuit addressing device

Publications (1)

Publication Number Publication Date
JPS59187850U true JPS59187850U (en) 1984-12-13

Family

ID=30210185

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8019283U Pending JPS59187850U (en) 1983-05-30 1983-05-30 memory circuit addressing device

Country Status (1)

Country Link
JP (1) JPS59187850U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4629198B2 (en) * 2000-08-18 2011-02-09 富士通セミコンダクター株式会社 Arithmetic apparatus and arithmetic method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4629198B2 (en) * 2000-08-18 2011-02-09 富士通セミコンダクター株式会社 Arithmetic apparatus and arithmetic method

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