JPS6087045U - microcomputer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

FIG. 1 and FIG. 2 are block diagrams showing one embodiment of the present invention, respectively, in which CPU: central processing unit, AND i
and AND2: AND gate circuit, OR1 and OR2 gate circuit, RAM 1 and RAM 2: readable/writable memory, DE: decoder, MUL: monostable multivibrator, l10 = input/output device, ROM: read-only memory, NL address Bus, DB: Data path, W:
Exit line for write command signal, R: Send line for read command signal.

Claims (1)

[Scope of utility model registration request] A monostable multivibrator that is started by an external input, a first AND gate circuit to which an oscillation output signal of this monostable multivibrator and a write command signal from a central processing unit are applied, and an output of this first AND gate circuit. an OR gate circuit to which signals and a read command signal from the central processing unit are applied, a decoder to which an address designation signal from the address bus is applied, and a signal corresponding to the write address of the external input is selected from among the output signals of this decoder. a second AND gate circuit to which the output signal of the OR gate circuit is applied; and a circuit to apply the output signal of the second AND gate circuit to a write and read command signal input terminal of the read/write memory. A microcomputer characterized by being equipped with.