JPS59134841U - information processing equipment - Google Patents
information processing equipmentInfo
- Publication number
- JPS59134841U JPS59134841U JP2697283U JP2697283U JPS59134841U JP S59134841 U JPS59134841 U JP S59134841U JP 2697283 U JP2697283 U JP 2697283U JP 2697283 U JP2697283 U JP 2697283U JP S59134841 U JPS59134841 U JP S59134841U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- processing unit
- central processing
- information processing
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のマイクロ・コンピュータに於ける中枢部
分の基本的構成を示すブロック接続図、第２図は本考案
に係る情報処理装置の一例の主要部を示すブロック接続
図、第３図及び第４図は、夫々、第２図に示される例の
動作説明に供される動作タイミングを表わす図である。
図中、１１はＣＰＵ、１２はＲＯＭ、１３はＲＡＭ。
１４はアドレス・バス・ライン、１５はデータ・バス・
ライン、１６はデコーダ、１８．２６及び２Ｂはオア・
ゲート、１９及び２５はアンド・ゲート、２０はカウン
タである。FIG. 1 is a block connection diagram showing the basic configuration of the central part of a conventional microcomputer, FIG. 2 is a block connection diagram showing the main parts of an example of an information processing device according to the present invention, and FIGS. FIG. 4 is a diagram showing operation timings for explaining the operation of the example shown in FIG. 2, respectively. In the figure, 11 is a CPU, 12 is a ROM, and 13 is a RAM. 14 is the address bus line, 15 is the data bus line.
line, 16 is the decoder, 18.26 and 2B are the or
Gates 19 and 25 are AND gates, and 20 is a counter.
Claims (1)
データを保持する第２のメモリ一部とが配されて、上記
中央処理部からのアドレス指定出力を上記第１及び第２
のメモリ一部の夫々に共通ニ伝達スるアドレス・バス・
ライ゛ンと、上記第１のメモリ一部からのプログラムを
構成する命令語の中央処理部への伝達及び上記中央処理
部と上記第２のメモリ一部との間のデータの伝達を行う
データ・バス・ラインとが設けられ、上記中央処理部か
らの読出し指示出力に対し、上記第１及び第２のメモリ
一部のいずれか一方を選択的に読出し状態となすメモリ
ー選択部が備えられて、上記第１及び第２のメモリ一部
のいずれの読出し状態に対するアドレス制御も上記アド
レス指定出力により行われるようにされた情報処理装置
。 、A central processing unit, a first part of memory that holds a program, and a second part of memory that holds data are arranged, and address designation output from the central processing unit is transmitted to the first and second memory parts.
An address bus that communicates common information to each part of the memory of
line, and data for transmitting command words constituting a program from the first memory part to the central processing unit and data transmission between the central processing unit and the second memory part. - a memory selection unit that selectively puts either one of the first and second memory portions into a read state in response to a read instruction output from the central processing unit; . An information processing apparatus, wherein address control for read states of both the first and second memory parts is performed by the address designation output. ,
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2697283U JPS59134841U (en) | 1983-02-25 | 1983-02-25 | information processing equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2697283U JPS59134841U (en) | 1983-02-25 | 1983-02-25 | information processing equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59134841U true JPS59134841U (en) | 1984-09-08 |
Family
ID=30157873
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2697283U Pending JPS59134841U (en) | 1983-02-25 | 1983-02-25 | information processing equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59134841U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57193847A (en) * | 1981-05-22 | 1982-11-29 | Matsushita Electric Ind Co Ltd | Memory bank dividing circuit |
-
1983
- 1983-02-25 JP JP2697283U patent/JPS59134841U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57193847A (en) * | 1981-05-22 | 1982-11-29 | Matsushita Electric Ind Co Ltd | Memory bank dividing circuit |
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