JPS618353U - Microcomputer with DMA data transmission line - Google Patents
Microcomputer with DMA data transmission lineInfo
- Publication number
- JPS618353U JPS618353U JP9151084U JP9151084U JPS618353U JP S618353 U JPS618353 U JP S618353U JP 9151084 U JP9151084 U JP 9151084U JP 9151084 U JP9151084 U JP 9151084U JP S618353 U JPS618353 U JP S618353U
- Authority
- JP
- Japan
- Prior art keywords
- dma
- data transmission
- microprocessor
- microcomputer
- bus line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Bus Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は本考案の一実施例を含むマイクロコンピュータ
システムのブロック図、第2図は従来のマイクロコンピ
ュータシステムのブロック図である。
図において、1・・・CPU、2,5・・・メモリ、3
,6・・・外部機器、4・・・バスライン、7・・・共
通バスライン、8・・・DMA用バスライン、9・・・
バス制御部、である。FIG. 1 is a block diagram of a microcomputer system including an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional microcomputer system. In the figure, 1...CPU, 2, 5...Memory, 3
, 6... External device, 4... Bus line, 7... Common bus line, 8... DMA bus line, 9...
This is a bus control unit.
Claims (1)
制御されるメモリと、前記マイクロプロセッサとの入出
力制御機能をもつ外部機器と、これら各部を共通接続す
る共通バスラインとを含むDMAデータ伝送路つきマイ
クロコンピュータにおいて、前記メモリおよび前記外部
機器のうちダイレクトメモリアクセス(DMA)データ
伝送を行う必要のあるメモリお・よび外部機器を共通接
続するDMA用バスラインと、このDMA用バスライン
および前記共通バスラインと接続されて前記マイクロプ
ロセッサの指示によりこのDMA用バズラインの制御を
するバス制御部とを備え、前記マイクロプロセッサの動
作と独立にDMAデータ伝送を行うことを特徴とするD
MAデータ伝送路つきマイクロコンピュータ。A microcomputer with a DMA data transmission line that includes a microprocessor, a memory controlled by the microprocessor, an external device having an input/output control function with the microprocessor, and a common bus line that commonly connects these parts, A DMA bus line that commonly connects the memory and the external device that require direct memory access (DMA) data transmission among the memory and the external device, and a DMA bus line that is connected to the DMA bus line and the common bus line. and a bus control section that controls the DMA buzz line according to instructions from the microprocessor, and performs DMA data transmission independently of the operation of the microprocessor.
Microcomputer with MA data transmission line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9151084U JPS618353U (en) | 1984-06-19 | 1984-06-19 | Microcomputer with DMA data transmission line |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9151084U JPS618353U (en) | 1984-06-19 | 1984-06-19 | Microcomputer with DMA data transmission line |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS618353U true JPS618353U (en) | 1986-01-18 |
Family
ID=30647463
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9151084U Pending JPS618353U (en) | 1984-06-19 | 1984-06-19 | Microcomputer with DMA data transmission line |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS618353U (en) |
-
1984
- 1984-06-19 JP JP9151084U patent/JPS618353U/en active Pending
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