JPS6040152U - data sampling circuit - Google Patents
data sampling circuitInfo
- Publication number
- JPS6040152U JPS6040152U JP13064783U JP13064783U JPS6040152U JP S6040152 U JPS6040152 U JP S6040152U JP 13064783 U JP13064783 U JP 13064783U JP 13064783 U JP13064783 U JP 13064783U JP S6040152 U JPS6040152 U JP S6040152U
- Authority
- JP
- Japan
- Prior art keywords
- data
- signal
- counter
- memory
- latch circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、本考案によるデータサンプリング回路の一実
施例を示す回路図、第２図は、第１図における主要個所
の信号の時間的関係を示すタイミングチャートである。
１・・・・・・シフトレジスタ、２・・・・・・ラッチ
回路、３・・・・・・メモリ、４・・・・・・カウンタ
、５・・・・・・デコーダ。FIG. 1 is a circuit diagram showing one embodiment of a data sampling circuit according to the present invention, and FIG. 2 is a timing chart showing the temporal relationship of signals at main points in FIG. 1. 1...Shift register, 2...Latch circuit, 3...Memory, 4...Counter, 5...Decoder.
Claims (1)
トで構成される直列データ信号を入力し、データのビッ
トクロック信号に同期して並列ｎビットデータ信号に変
換するシフトレジスタと、このシフトレジスタからの並
列ｎビットデータをラッチするラッチ回路と、前記ラッ
チ回路の出力データを格納するメモリと、前記ピットク
ロック信号を計数し、ｎカウント毎に、前記ラッチ回路
を動作させると共に前記メモリに対し書込み信号および
アドレス信号を供給するカウンタと、このカウンタの計
数出力を入力し、計数値が（Ｎ−１）Ｘｎ＋ｍの時、こ
のカウーンタに対しそれぞれ強制的にＮＸｎに変換、す
るように制御するデコーダとを備えたデータサンプリン
グ回路。a shift register that inputs a serial data signal in which the Nth data word is m bits and the other data words are n bits, and converts it into a parallel n-bit data signal in synchronization with a data bit clock signal; A latch circuit that latches parallel n-bit data from the shift register, a memory that stores the output data of the latch circuit, and a memory that counts the pit clock signal and operates the latch circuit and stores it in the memory every n counts. A counter that supplies a write signal and an address signal, and the count output of this counter are input, and when the count value is (N-1)Xn+m, the counter is controlled to be forcibly converted to NXn. A data sampling circuit with a decoder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13064783U JPS6040152U (en) | 1983-08-24 | 1983-08-24 | data sampling circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13064783U JPS6040152U (en) | 1983-08-24 | 1983-08-24 | data sampling circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6040152U true JPS6040152U (en) | 1985-03-20 |
| JPH0117880Y2 JPH0117880Y2 (en) | 1989-05-24 |
Family
ID=30295630
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13064783U Granted JPS6040152U (en) | 1983-08-24 | 1983-08-24 | data sampling circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6040152U (en) |
-
1983
- 1983-08-24 JP JP13064783U patent/JPS6040152U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0117880Y2 (en) | 1989-05-24 |
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