JPH0117880Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a data sampling circuit, and particularly to a data sampling circuit when input data includes a data word having a different word length.

[Background technology]

In data processing, data is generally processed in so-called data words having a certain bit length (for example, bytes). However, when this is to be transmitted, it is subjected to parallel-to-serial conversion on the transmitting side and sent out as a serial bit sequence to the transmission line. On the receiving side, the delimiter of each data word is identified in the serial bit sequence, and the data is restored by performing parallel-to-parallel conversion. In such a transmission system, the data sampling circuit on the receiving side processes all data words as having the same bit length, so if there are data words with a different bit length than other data words, the data sampling circuit will process the data words as having the same bit length. The separation between the lines may be off, making accurate playback impossible. Therefore, if it is necessary to include a data word with a different word length, the remaining part is padded with zeros to make the word lengths the same before transmission. In that case, of course, the receiving side must remove the padded zeros.

If all data word lengths are the same as described above, the circuit configurations on both the transmitting and receiving sides are simple.

However, on the other hand, the work of aligning the word lengths on the sending side and the decomposition work on the receiving side are as follows:
Both are done by programs and depend on the CPU.

Recently, in various data transmission systems, there has often been a demand to free the above-mentioned terminal data processing work from the busy hands of the CPU.

[Disclosure of invention]

SUMMARY OF THE INVENTION In order to meet the above requirements, it is an object of the present invention to provide a data sampling circuit that can receive serial bit sequences containing data words of different word lengths and process them without depending on the CPU.

The data sampling circuit according to the present invention inputs data in a serial bit sequence and
A shift register that performs parallel conversion, a latch circuit that locks parallel data from the shift register,
A data stream is formed by a memory that stores the locked data at a specified address.

Furthermore, if the Nth data word of the above input data has a word length of m bits, and the word lengths of the other data words are n bits, then the data sampling circuit according to the present invention In order to control the flow of data, a counter is provided to count the bit clocks of the input signal, and a decoder is provided to decode the output of the counter.

The counter provides a latch clock signal to the latch circuit every n counts. The counter also supplies the memory with an address that increases by 1 every n counts and a write signal.

The decoder is connected to input the output of the counter so that when the count is (N-1)×n+m, the count of the counter is forced to be N×n.

As a result, in the data sampling circuit with the above configuration, a data word having a word length of m bits is
Even if the data is mixed in a string of other n-bit data words, the data can be restored without any program processing, and the load on the CPU is reduced.

Furthermore, since the circuit configuration is simple, it is easy to manufacture and suitable for mass production.

[Best form for implementing the idea]

FIG. 1 is a circuit diagram showing an embodiment of a data sampling circuit according to the present invention.

FIG. 2 is a timing chart showing the temporal relationship of signals of the main parts in FIG. 1.

In FIG. 1, a serial bit sequence IDATA+ is input to the IN terminal of shift register 1.
As shown in FIG. 2, IDATA+ is assumed to have a length of 6 bits only in the second data word, and all others to have a length of 8 bits (bytes).

A data bit clock signal DTCLK+ is supplied to the clock (CK) terminal of the shift register 1.

The shift register is the data signal (IDATA) 8
Send the bits (QA to QH) to the input terminals 1D to 8D of the latch circuit 2. As will be described later, the latch circuit 2 receives a clock (CK) signal from the output signal of the counter 4, and is controlled thereby to send 8-bit data 1Q to 8Q to the input terminals D0 to D7 of the memory 3.

The memory 3 stores the input data at the address specified by the address signals A0 to A4 supplied from the counter 4 in response to a write signal also supplied from the counter 4.

The flow of input data through the shift register 1, latch circuit 2, and memory 3 described above is controlled by the counter 4 and decoder 5 as follows.

The counter 4 is supplied with, as its clock (CK) input, a signal DTCLK- (see FIG. 2) obtained by inverting the input data bit clock DTCLK+ by an inverter 6.

This counter 4 has eight output terminals QA (LSB) to QH (MSB).

In addition, counter 4 has a low level (“L”) on the LD terminal.
When the signal is input, the input to terminals A to H becomes
They are sent out from corresponding output terminals QA to QH. Terminals A to H are all grounded except for terminal E, which is connected to +V. In other words, LD is “L”
Then, only the output of QE is "H" (1), and the other outputs are "L" (0).

The output terminal QC of the counter 4 is connected to the clock (CK) input of the latch circuit 2 via an inverter 7.

The output terminal QB of the counter 4 and the output terminal of the inverter 7 are connected to a NAND gate 8.
The output of this NAND gate 8 serves as a write signal for the memory 3.

Output terminals of counter 4 QD, QE, QF, QG,
QH is the address input terminal of memory 3, respectively.
Connected to A0, A1, A2, A3, and A4.

Output terminals QA to QH of the counter 4 are connected to input terminals A to H of the decoder 5.

When the decoder input (counter 4 count) reaches 13, the decoder output terminal Y13 outputs
Sends out a signal that becomes “L”. This signal is applied to the load (LD) terminal of the counter 4.

Next, the operation of the data sampling circuit will be explained with reference to FIGS. 1 and 2.

As already mentioned here the input data
The second data of IDATA+ is defined as having a 6-bit configuration, and the others are defined as having an 8-bit configuration.

Therefore, input data IDATA+ is taken into shift register 1 in accordance with bit clock signal DTCLK+, converted into parallel data, and sent to latch circuit 2. Since the clock input (CK) of the latch circuit 2 is supplied with the inverted signal of the output of the output terminal QC (third digit) of the counter 4, the latch circuit 2 latches the input data at the falling edge of the signal QC. .

As a result, the first data is latched and sent to the memory 3 when the eighth bit (seventh in FIG. 2) is captured. The latched 8-bit data is held in the latch circuit until the next latching is performed.

By the way, the address of memory 3 is the counter's address.
When the output of QD becomes "H" (1) (that is, at count 8), A0=1, and the first is designated. QD output becomes “H”, then QB
When is “H” and QC is “L”, NAND gate 8
The output of the memory becomes "L", the write signal of the memory becomes "L", and the first 8 bits of data are written to address 1 of the memory 3.

Meanwhile, the second data is being sent from the shift register 1 to the latch circuit 2.

On the other hand, when the count of the bit clock signal by the counter 4 reaches 13, the output terminal of the decoder 5
The signal (LD) applied to the LD terminal of the counter from Y13 becomes "L". This forces the output of the counter to be (LSB) 00001000 (MSB). In other words, the count is forcibly increased to 16.

As a result, the output QC of the counter 4 falls, and the latch circuit 2 latches the data at that point and sends it to the memory 3.

Address signals A4 to A0 of the memory 3 become 0010 and specify address 2. And the write signal is “L”
Then, 8-bit data is written to address 2 of memory 3. The upper 2 bits of the first data are written as they are to the lower 2 bits of the data written at address 2, but no data shift occurs.

Thereafter, the third and subsequent data are taken in, and every 8 counts of counter 4, 3rd and subsequent data of memory 3 are taken in.
Stored after the address.

As described above, in the data sampling circuit according to the present invention, when the Nth data word is composed of m bits and all other data words are composed of n bits,
To enable data restoration of serial bit sequence data signals without placing any burden on the CPU.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of a data sampling circuit according to the present invention, and FIG. 2 is a timing chart showing the temporal relationship of signals at main points in FIG. 1. 1...Shift register, 2...Latch circuit, 3
...Memory, 4...Counter, 5...Decoder.

Claims (1)

[Scope of utility model registration request] A shift register receives a serial data signal in which the Nth data word is m bits and the other data words are n bits, and converts it into a parallel n-bit data signal in synchronization with the data bit clock signal; A latch circuit that latches parallel n-bit data from a register, a memory that stores the output data of the latch circuit, and a memory that counts the bit clock signal and operates the latch circuit and writes data to the memory every n counts. a counter that provides signals and address signals;
Input the count output of this counter, and the count value is (N
-1) A data sampling circuit comprising a decoder that controls this counter to forcibly convert it to Nxn when it is xn+m.