JPS6335143B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for receiving a plurality of serial signals having different word lengths.

Conventionally, as shown in FIG.
DS ₁ …If DS ₃ exists, data line (DATA) and control line (CONTROL) and command stage depending on the number of stages.
There is a drawback that CS ₁ ... CS ₃ ) is required.

Furthermore, with the configuration shown in Figure 2, the number of data lines and control lines can be reduced, but with this conventional configuration, even if the word lengths of the data stages are different, words of the same length can be transmitted from the data lines and control lines. When serial data is received, redundant data is ignored in the data stage with a short word length, resulting in poor transmission efficiency.

The present invention has been made to solve these conventional problems, and the amount of information is sent from the sending side and consists of multiple pieces of information data with different word lengths depending on the frequency of use and fixed length commands. When a receiving side receives a serial signal, a data line and a control line are provided between the receiving side and the transmitting side, and a first data stage with a long word length and a second data stage with a short word length are provided on the receiving side. A data stage and a command stage for selecting the first and second data stages by the command are provided, a command for controlling the command stage is incorporated into the serial signal on the transmitting side, and the amount of information is determined by the word length. When the first information data consists of a long first information data, a data write signal is received via the control line at a predetermined clock position, and the command stage is controlled by a command at a clock position corresponding to the received data write signal. When first information data with a long word length is loaded into the first data stage and the amount of information consists of second information data with a short word length, a data write signal is sent via the control line at a predetermined clock position. and controls the command stage with a command at a clock position corresponding to the received data write signal to input second information data with a short word length into the second data stage, and control the command stage with a command at a clock position corresponding to the received data write signal. It is an object of the present invention to provide a serial signal receiving method characterized in that a plurality of pieces of information data each having a different amount of information are outputted by the command stage.

Hereinafter, preferred embodiments of the present invention will be described in detail based on the drawings.

In the embodiment shown in FIG. 3, the amount of information consists of a plurality of information data with different word lengths depending on the frequency of use and a fixed length command, and a data line DATA and a control line are connected between the sending side and the receiving side.
There is a WR. Data line from sender
The receiving system S receives the serial signal sent from DATA and the data write signal sent from control line WR.

IS is the interface stage, CS is the command stage, DS ₁ is the first data stage with a long word length (the data is called first information data), DS ₂ ,
DS ₃ is a second data stage (the data is referred to as second information data) with a short word length, and the shift register SR ₁ of the command stage CS and the shift registers SR ₂ and SR ₃ of the data stage DS ₁ are Cascaded.

IV is an inverter, A ₁ to _{A 6} are AND gates,
_SR4 to _SR5 are shift registers, _L1 to _L2 are latch registers, and BG is a blanking gate.

Also, DATA is a data line and WR is a control line. When the control line WR becomes "1", it means that a data write signal has been transmitted. The data write signal has an n×4 bit configuration, and less than 4 bits are limited to “0001”. "0001"
No data is sent to the data line DATA when the data write signal is being sent. 4-bit synchronization and clock synchronization are obtained from the data write signal. Note that "0001" becomes "1000" on the time axis. Also, CP is a clock pulse. On the output side, OUT ₁ to _{OUT 3} are the received outputs of each data stage.

Now, when the interface stage IS receives data from the data line DATA and a data write signal from the control line WR, it regards the data in the first four bits of the data write signal as a command. This command becomes invalid when the data write signal ends. Data stage DS ₁ ~ by command stage CS controlled by this command
Select DS ₃ to produce the desired outputs OUT ₁ to _{OUT 3} at the given data stage.

That is, each data stage DS ₁ to DS ₃ is input to one input terminal of each AND gate A ₃ to _{A 6} by the command stage CS, and the AND gate of the interface stage IS is input to the other input terminal. Valid data outputs OUT ₁ to OUT ₃ occur only when the output of A ₁ is applied.

In this embodiment, the configuration of each data stage is different. That is, in data stage DS ₁ , shift register SR ₁ of command stage CS and shift registers SR ₂ and SR ₃ of data stage DS ₁ are connected in cascade.

Furthermore, data stages DS ₁ , DS ₂ , and DS ₃ are circuits that output received data in parallel, and data stages DS ₁ and DS ₃ simultaneously output parallel output with respect to the time axis. Data stage DS ₂ outputs data randomly in parallel to the time axis.

For example, assume that the first information data has an 8-bit configuration and the second information data has a 4-bit configuration, and that the first information data is transmitted. In this case, the unit frame consists of 8 bits of first information data,
4-bit command, 4-bit data write signal
It has a 16-bit configuration. Note that data write signal 4
No data is sent to the clock position corresponding to the bit. When the data write signal "0001" is transmitted ("1000" on the time axis), the first 4 bits of data "1000"("0001" on the time axis) are identified as a command. Therefore, at clock position _t13 of clock pulse CP shown in FIG.
Among the data stored in SR ₁ , SR ₂ , and SR ₃ , the data in shift register SR ₁ is used as a command, and the data in shift registers SR ₂ and SR ₃ are used as first information data, and AND gates A ₁ and A ₂ are activated. becomes. In other words, AND gates _A1 and _A2 are activated by "1000" of shift register SR ₁ and "0001" of the data write signal ("1000" and "1" on the time axis correspond to clock position _t13 ). Become. As a result, the first information data of shift registers SR ₂ and SR ₃ are transferred to latch registers L ₁ and L ₂ and output in parallel from output OUT ₁ . When the data write signal "0001" ends, the command "1000" of shift register SR ₁ becomes invalid at clock position _t16 , and the next data is stored in shift registers SR ₁ , SR ₂ , SR ₃ or SR ₄ , SR ₅ . do.

On the other hand, shift registers SR ₁ , SR ₄ , and SR ₅ are connected in parallel. The second information data has an 8-bit configuration consisting of 4 bits of command and 4 bits of data write signal. In this case, the data write signal "1111" is received at clock positions _t5 to _t8 . As a result, the first 4-bit data "0100" becomes the command. When the data write signal is "1111", the data line DATA is sent to the corresponding clock position _t5 to _t8 .
The second information data is inputted via. The shift register SR ₁ command is an AND gate using the data write signal “1111” and clock pulse CP.
Locked for "1111" by A ₂ . On the other hand, the AND gate _A1 operates according to the AND logic of "1111" and the clock pulse CP, and the output of the AND gate _A1 becomes a signal corresponding to the clock pulse CP. This signal is input to AND gate _A4 as a shift pulse. The second information data is shifted into the shift register SR ₄ by AND logic with " ₁ " of the command "0100" fixed in the shift register SR 1. In this case, the parallel output of output OUT ₂ is random with respect to the time axis. When you want to output in parallel to the time axis, the command is "0010", so the AND gate _A5 is activated by the AND logic of this command "1" and the data write signal "1111". Therefore, the second blanking gate BG
The information data is output in parallel from the output OUT ₃ at the end of the data write signal "1111", that is, at clock position _t9 (not shown).

FIG. 4 shows another embodiment, in which the command register CREG and the data register DREG1 are connected in cascade. DREG2 is a command register
This is a data register connected in parallel to CREG. CDEC and DDEC are registers CREG and
Parallel signal CDATA, DDATA from DREG1
This is a decoder that captures A ₁ to A ₈ are and
It is a gate.

Now, when the control line WR is "0", the shift clock (CLOCK) is an AND gate.
When applied to A ₁ , when a serial signal is input to the data line DATA by the AND gate A ₁ , parallel signals CDATA, DDATA are sent from the control register CREG and data register DREG.
are added to decoders CDEC and DDEC, respectively.

Therefore, only when the output conditions of decoders CDEC and DDEC are met, the control line WR
becomes "1" and the data line signal is received.
This data line signal and the clock position of the bit corresponding to the data line signal become a command and are output by AND gates A ₂ , A ₄ and A ₅ to _{A 8.}
Information data is output from OUT ₅ to _{OUT o} .

Next, when the amount of information consists of frequently used data, the data taken into the command register CREG is output as a parallel signal CDATA and input to the decoder CDEC. At this time, when the control line WR becomes "1", the AND gate is activated.
A shift clock (CLOCK) is applied via _A3 , and serial data is input to the data register DREG2 to obtain desired outputs _OUT1 to _OUT4 .

Also, in Figure 3, the command stage CS
Since the command obtained is equivalent to 2 ⁴ , the number of data stages can be increased according to the number of commands, and the terminal S ₁ of data stage DS ₁ ~
The amount of received information can be increased simply by adding shift registers in cascade to terminals S ₄ and S ₅ of S ₃ or data stage DS ₂ , respectively.

As is clear from the above embodiments, the serial signal receiving system according to the present invention is capable of transmitting signals from the transmitting side, in which the amount of information consists of a plurality of pieces of information data with different word lengths depending on the frequency of use and fixed length commands. When receiving a serial signal on the receiving side,
A data line and a control line are provided between a receiving side and a transmitting side, and the receiving side is provided with a first data stage having a long word length, a second data stage having a short word length, and the first and second data stages. a command stage for selecting a data stage by the command, a command for controlling the command stage is incorporated into the serial signal on the transmitting side, and when the amount of information consists of first information data having a long word length, receiving a data write signal via the control line at a predetermined clock position;
The command state is controlled by a command at a clock position corresponding to the received data write signal, and the first information data having a long word length is loaded into the first data stage, and the second information data having a short word length is loaded into the first data stage. , the data write signal is received via the control line at a predetermined clock position, and the command stage is controlled by a command at the clock position corresponding to the received data write signal, so that the second The second information data with a short word length is taken into the data stage, and the command stage controlled by the command outputs a plurality of pieces of information data each having a different amount of information. Serial signals can be received with high transmission efficiency by using multiple data stages together, and the number of lines does not have to be increased. It has the effect of building a digital system.

[Brief explanation of the drawing]

1 and 2 are conceptual diagrams showing a conventional serial signal receiving method, FIG. 3 is a circuit diagram of one embodiment to which the serial signal receiving method according to the present invention is applied, and FIG. 4 is a circuit diagram of another embodiment. FIG. 5 is a diagram showing the timing of signals in each part of the circuit shown in FIG. 3. DS ₁ ...first data stage, DS ₂ , DS ₃ ...
...Second data stage, CS...Command stage.

Claims (1)

[Claims] 1. When the receiving side receives a serial signal sent from the transmitting side, which consists of multiple pieces of information data with different word lengths depending on the frequency of use and fixed-length commands, the communication between the receiving side and the transmitting side is A data line and a control line are provided between them, and on the receiving side, a first data stage with a long word length, a second data stage with a short word length, and the first and second data stages are selected by the command. a command stage for controlling the command stage; the transmitting side incorporates the command for controlling the command stage in the serial signal; A data write signal is received via a control line, the command stage is controlled by the command at a clock position corresponding to the received data write signal, and first information data with a long word length is transferred to the first data stage. When the amount of information consists of second information data with a short word length, a data write signal is received via the control line at a predetermined clock position, and a clock position corresponding to the received data write signal is read. The command stage is controlled by a command, second information data with a short word length is taken into the second data stage, and the command stage controlled by the command generates a plurality of information data each having a different amount of information. A serial signal reception method characterized by outputting .