JP2849804B2 - Memory access interface circuit and memory access method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an interface circuit and an access method, and more particularly to an interface circuit and a memory access method for memory access.

[0002]

2. Description of the Related Art Conventionally, there are two types of methods for reading memory data: a serial type and a parallel type. FIG. 9 is a block diagram of a conventional circuit for reading memory data in a serial manner. The read circuit shown is a shift register 2
, A decode memory element 3 and an output register 4. Data to be read is stored in the decode memory element 3. This decode memory element, together with the shift register 2 and the output register 4, is connected to pins AIN and D
OUT, CLK and CS ↓ (in this specification, ↓ is used to mean that the active input of the pin is L).

FIG. 10 is a timing chart of FIG. 9. Hereinafter, a serial reading operation will be described with reference to FIGS.

[0004] CS ↓ is the IC package 1 (that is, I
The enable pin (L level) for activating the circuit located in C1) is received, the CLK pin receives the time pulse signal, and the AIN pin is used to receive the address signal. Here, if each address of the decode memory element 3 is 14 bits, the AIN pin receives 14 address signals A0 to A13 in a serial manner of 1 bit, and accordingly, the shift register 2 also sequentially receives A0 to A13. -A
13 is received. Then, after A0-A13 is completely received, A0-A13 is output again to the decode memory element 3, and after these are received by the decode memory element 3,
At the same time as decoding, the data D0-D7 stored in the addresses A0-A13 are output to the output register 4, and the output register 4 outputs D0-D7 in a bit-by-bit serial manner via the pin DOUT.

An advantage of the serial reading method is that the interface circuit for reading the decode memory element 3 requires only one address pin and one data output pin. Therefore, when the memory capacity of the decode memory element 3 is expanded, the number of bits of the input address only needs to be increased, and the number of pins of the IC package 1 does not need to be changed. No need to change. Further, the cost of the package can be saved, and the number of signals required for controlling the memory IC can be reduced.

However, the serial type reading speed is extremely slow, and it takes one clock time to write one bit or read one data bit, which is extremely time consuming. It had been.

In addition, when the bit difference between the two address signals before and after is not large, for example, when only 8 bits are different between two 32-bit address signals, the subsequent address signal is not read by the serial reading method. Unless all of the 32 bits have been input, the data indicated by the subsequent address signal cannot be read, and only the modified 8 bits cannot be input. This is because the input of the address signal and the output of the data signal are controlled by a single fixed time pulse signal (CLK in FIG. 10), so that when the address signal has a different number of bits, the external peripheral control circuit This is because the time for writing the address and the time for reading the data cannot be adjusted.

In the case of a simple memory data reading method, all data to be read are usually stored at consecutive addresses in the decode memory element, and even if the preceding and succeeding address signals are discontinuous, usually a small number of data are read. In this case, the serial reading method is disadvantageous in terms of speed when there are many continuous inputs of continuous address signals or input of an address signal having a very small difference in address bits.

FIG. 11 is a block diagram of a conventional circuit for reading memory data in parallel. FIG. 11 shows the decode memory element 5, and the difference from FIG.
Since the 4-bit address signal is simultaneously input to the decode memory element 5, and after decoding, the data stored at the address indicated by the address signal is simultaneously output again, the decode memory element 5 has 14 address receiving pins A0-A13. , And eight data output pins D0-D7
And the decode memory element 5 further includes a chip-selection pin CS ↓
And an output-enabling pin OE ↓. FIG. 12 shows the signal timing of each pin of the circuit in FIG.

[0010] The advantage of the parallel type is that, since both the address and data of each bit are received or output by the corresponding pins, complete data can be obtained by one reading and the reading speed is high. It is in.

However, the disadvantage is that there are too many pins,
The cost of the package increases. In addition, since an external controller for controlling the decode memory element 5 must control these address pins and data pins using a considerable number of pins, the number of control pins of the controller increases. Further, once the decode memory element 5 is expanded, the number of pins of the entire decode memory element 5 increases, so that the external peripheral control system must be laid out and designed again.

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, it is a main object of the present invention to provide a memory access interface circuit and a memory access method for effectively improving the access speed of memory data.

Another object of the present invention is to provide a memory access interface circuit and a memory access method which can effectively reduce the number of pins of a memory and the cost of a package.

[0014]

In order to achieve the above object, an interface circuit for memory access according to the present invention is an interface circuit for reading data from a decode memory element having a plurality of addresses, each address corresponding to one data. And one of the decode memory elements which are serially input from the outside several times.
An address storage circuit for storing an address signal and outputting the address signal to the decode memory element at the same time; and a data output buffer circuit for temporarily storing the data of the decode memory element stored at the address indicated by the address signal A bit selection circuit connected to the address storage circuit and the data output buffer circuit, the bit selection circuit setting the number of bits that the address storage circuit can receive simultaneously and the number of bits that the data output buffer circuit can output simultaneously; A control circuit that is connected to the address storage circuit and the data output buffer circuit, and that outputs an enabling signal input to the address storage circuit and the data output buffer circuit, and a read / write signal input to the decode memory element; And some of the address / data pins are
External address for dividing and transferring the address and data
The plurality of addresses / data are electrically connected to a controller.
The number of tap pins is set by the bit selection circuit.
It is determined according to the specified number of bits .

[0015] The decode memory element is a read-only storage device, and the address storage circuit is preferably connected to the control circuit and the decode memory element.
An address counter for storing the address signal, connected to the bit selection circuit, the address counter and the control circuit, and generating a plurality of address pointer signals based on the number of bits set in the bit selection circuit; Providing the address pointer signal each time an address signal of the decode memory element is input,
An address pointer generator, wherein the address counter serves as an address pointer necessary for storing the address.

Preferably, the data output buffer circuit is connected to the control circuit and the decode memory element,
A one-way data buffer for storing data stored at an address in the decode memory element indicated by the address signal and serially outputting the divided data in several times, the bit selection circuit, the data buffer, The data buffer is connected to the control circuit and generates a plurality of data output pointers based on the number of bits set in the bit selection circuit. A data pointer generator for determining a data bit for each degree to be output by the buffer.

Here, the number of bits of the address received at one time by the address storage circuit is smaller than the number of bits of the address of the decode memory element, and the number of bits of data output at one time by the data output buffer circuit is It is smaller than the number of bits of data stored in each address of the decode memory element.

The memory access interface circuit according to the present invention for achieving the above object is an interface circuit for accessing data of a decode memory element having two states of reading and writing. The address memory circuit that stores the address signal of the decode memory element that is serially input several times and outputs the address signal to the decode memory element at the same time, and the interface circuit is in a read state. A data buffer circuit for temporarily storing the data of the decode memory element stored at the address indicated by the address signal, and conversely, for temporarily storing externally input data when the interface circuit is in a write state; The address storage circuit and the data buffer circuit. Connected to the number of bits that can be received simultaneously by the address storage circuit, and a bit selection circuit that sets the number of bits that can be output simultaneously by the data buffer circuit, connected to the address storage circuit and the data buffer circuit, Outputting an enable signal input to the address storage circuit and the data buffer circuit, and a read / write signal input to the decode memory element,
A control circuit for generating a signal for controlling the interface circuit, wherein a plurality of address / data pins are provided.
A part of the address and the data are divided and transferred.
Electrically connected to an external controller for
The number of dress / data pins is determined by the bit selection.
It is determined according to the number of bits set by the circuit .

The decode memory element is a random access memory element, and the address storage circuit is preferably connected to the control circuit and the decode memory element, and stores an address counter for storing the address signal; A plurality of address pointer signals are generated based on the number of bits set in the bit selection circuit connected to the circuit, the address counter and the control circuit, and each time an address signal of the decode memory element is input from outside. An address pointer generator for providing the address pointer signal, the address counter being an address pointer necessary for storing the address.

The data buffer circuit is preferably connected to the control circuit and the decode memory element, and when the interface circuit is in a reading state,
The data stored in the address in the decode memory element indicated by the address signal is temporarily stored, and the data is serially output to the outside several times, and conversely, the interface circuit is in a write state. Occasionally, data that has been input from the outside divided into several times is stored at one time,
A two-way data buffer in which the data is written to an address in the decode memory element indicated by the address signal; and a bit selection circuit, the two-way data buffer and the control circuit, By providing a data output pointer signal to the two-way data buffer based on the number of bits set in the bit selection circuit, the output / input data bits to be output each time by the two-way data buffer are determined. A data pointer generator.

The number of bits of an address received by the address storage circuit at one time is smaller than the number of bits of an address of each of the decode memory elements, and the number of data bits input and output by the data buffer at one time is equal to the number of the decode memory elements. Is smaller than the number of bits of data corresponding to each address.

Further, in order to achieve the above object, the memory reading method of the present invention comprises a plurality of address / data pins.
Part of the address and data is divided and transferred
Is electrically connected to a controller external to the plurality of addresses.
The number of the part of the data / data pins is determined by a bit selection circuit.
Determining according to the set number of bits , sequentially receiving and storing a part of the address signal from outside until a signal for one address of the decode memory element is completely stored; transmitting a signal at a time to the de <br/> code memory device, receiving stored once data address indicated by the address signal from said decoding memory device, the data of the address which the address signal indicates the Sequentially outputting a part of the data to the outside until the data is completely output.

[0023] In order to achieve the above object, the writing method of the present invention decode memory device includes a plurality of address
/ Some of the data pins split the address and data
Electrically connected to an external controller for transferring,
The number of said part of the plurality of address / data pins is represented by bits
A switch determined according to the number of bits set by the selection circuit
Step and until said one address signal decoding memory element is completely stored, the method comprising: sequentially receiving stores some of the address signal from the outside, the data to be stored in the address which the address signal indicates complete Sequentially receiving and storing a part of the data from the outside until the data is stored in the decode memory element, and writing the data at once to an address in the decode memory element indicated by the address signal.

[0024]

BRIEF DESCRIPTION OF THE DRAWINGS Other objects, structural features and effects of the present invention can be better understood by describing the embodiments with reference to the accompanying drawings. Of course, the present invention is not limited to these embodiments, and it goes without saying that various modifications and changes are allowed without departing from the technical idea of the present invention and the scope of the appended claims.

FIG. 1 is a block diagram showing a preferred embodiment of a memory reading interface circuit 6 according to the present invention. The interface circuit 6 is for reading data from the decode memory element 11. The interface circuit 6 includes a control circuit 7, an address storage circuit 8, a bit selection circuit 9, and a data output buffer circuit 10. Have been. The address storage circuit 8 includes an address counter 13 connected to the control circuit 7 and the decode memory element 11, and an address pointer generator 12 connected to the bit selection circuit 9, and the data output buffer circuit 10 One-way data buffer 14 connected to control circuit 7 and decode memory element, bit selection circuit 9, one-way data buffer 14 and control circuit 7
And a data pointer generator 15 connected to the data pointer. The decode memory element 11 used in the present embodiment is a read-only storage device (ROM).

The decode memory element 11, the control circuit 7, the address circuit 8, the bit selection circuit 9,
The same IC package 61 as the data output buffer circuit 10
This IC 61 is connected to pins WR ↓, R
D ↓, CS ↓ and address / data pins ADo to ADn. In this embodiment, n = 7.

[0027] In the operation of FIG. 1, a n is 7, then each address decoding memory element 11 and 32 bits, and it is assumed that 16-bit data is stored in each address, ADo～AD ₇ is If used completely, only at most 8 bits of address signal can be input from the outside at one time, so 4 times (8 bits / time)
After the input, the input of the 32-bit address signal is completed. At this time, the bit selection circuit 9 generates a plurality of address pointers in the address pointer generator 12 based on the n value, and when the first set of 8-bit addresses is input to AD _{0 to} AD ₇ , the control circuit 7 Causes the address pointer generator 12 to transmit the first address pointer to the address counter 13 so that the address counter 13 generates the first set of addresses based on the address indicated by the first address pointer. An 8-bit address is stored therein. Thereafter, when the second set of 8-bit addresses are input to AD _{0 to} AD ₇ , the address pointer generator 12 causes the second address pointer to be transmitted to the address counter 13.
Stores a second set of 8-bit addresses therein based on the address pointed to by the second address pointer. Thus, when the 32-bit address signal is completely stored in the address counter 13, the control circuit 7 causes the address counter 13 to transmit the 32-bit address signal to the decode memory element 11,
These address signals are decoded by setting the decode memory element 11 to a usable state (enable). At the same time, the decode memory element 11 stores the 16-bit data corresponding to the one address signal in a one-way buffer 14 in parallel.
And the bit selection circuit 9 also generates a plurality of data output pointers for the data pointer 15 based on the n value, while the control circuit 7 outputs the data pointer generator 1
5, the first data output pointer is transmitted to the one-way data buffer 14, and the data bits to be output by the one-way data buffer 14 are controlled each time. At this time, since n = 7, the data buffer 14 has 16-bit data.
The reading of one address data is completed by outputting the bit data in two steps before and after AD _{0 to} AD ₇ .

FIG. 2 is a timing chart of each pin of FIG. 1. When CS ↓ is LOW, the circuit of the IC 6 becomes operable, and when WR ↓ is LOW, input of an external address signal is permitted. When RD ↓ is LOW, data output is allowed. Here, A _{0 to} A _{2n + 1} represent address bits, and D _{0 to} D _{2n + 1} represent data bits.

According to the present invention, the two signals WR ↓ and RD ↓ are given to control the timing of writing the address signal and the timing of reading the data, respectively, so that the external peripheral control circuit is changed based on the actual address. Since the timing of writing the address signal and reading the data can be adjusted in a timely manner, the following advantages are provided.

After the data of one set of address signals is completely read, the address counter is automatically incremented,
The address of the next decode memory element 11 is directed.
Therefore, if the data to be read by the external peripheral controller is continuous address data, after the data indicated by the first set of addresses is read, the external peripheral controller repeatedly inputs a signal to RD ↓. It is sufficient to directly read the data indicated by these continuous addresses, and there is no need to write subsequent address signals again. In this way, a large amount of address writing time can be saved.

Each time one address signal is completely written, WR ↓ becomes HIGH. At this time, the address pointer generator 12 is cleared to 0 by the control circuit 7. On the other hand, after the data pointed to by one address signal is read, RD ↓ becomes HIGH, and the data pointer generator 1
5 is cleared to 0 by the control circuit 7. Therefore, IC
When there is a difference only in the low bit of the bit of the address signal input from the external controller, the different low bit input from the external controller is used as the address counter 1
Written at the low bit position of 3 (because the address pointer generator 12 has already been cleared to 0). At this time, since the address stored in the address counter 13 is the desired next one address, there is no need to write the invariable high bit of the address signal again, and RD ↓ is set by an external controller. If LOW, the reading operation can be started.

FIG. 3 is a timing chart of each pin when n = 7 in FIG. In the figure, A _{0 to} A ₃₁ indicate address bits, and D _{0 to} D ₁₅ indicate that they correspond to the data of the first part and the data of the second part of A ₀ and A ₃₁ .
FIGS. 4 and 5 show timing charts of the respective pins when n = 3 and 0 in FIG.

Even when eight address / data pins are provided, if some of the pins, for example, four or one pin, are connected to an external control circuit, the effect is as follows. The effect is the same as when four or one pins are used.

FIG. 6 is a diagram showing a preferred embodiment of the memory access interface circuit according to the present invention.
The interface circuit 25 is for accessing data in the decode memory element 20. The interface circuit 25 includes a control circuit 16, an address storage circuit 17, a bit selection circuit 18, and a data buffer circuit 19. The address storage circuit 17 comprises an address counter 21 and an address pointer generator 22, and the data buffer 19 is a two-way data buffer 2.
3 and a data pointer generator 24. The difference between the present embodiment and the embodiment of FIG. 1 is that the decode memory element 11 of the embodiment of FIG. 1 is a read-only storage device (ROM), whereas the decode memory element 20 of FIG. Memory (RA
M). Therefore, the interface circuit 25 in the present embodiment has two states of reading and writing. Also, while the one-way data buffer is used in FIG. 1, the embodiment of FIG. 6 uses a two-way data buffer.

In order to enable a write state in this embodiment, one pin S is provided in the control circuit 16 of FIG.
More ADs are provided than in the embodiment of FIG. When the interface circuit 25 is in the reading state, the SAD
Does not operate, and each circuit in the IC 26 operates the same as in FIG.

When the interface circuit 25 is in the write state, the SA is used to distinguish whether the write signal is an address signal or a data signal.
D has two states (HIGH, LOW). For example, SA
When D is HIGH, an externally input signal is an address signal, and when SAD is LOW, an externally input signal is a data signal. In the process of inputting the address signal, it is stored in the address counter 21 in the same manner as in the embodiment of FIG. If the input signal is a data signal, the control circuit modifies the signal transmission direction of bidirectional data buffer 23, data stored inside the through AD ₀ to AD _n externally bidirectional data buffer 23, The data is transmitted to the decode memory element 20 and written to the address indicated by the address counter.

The present invention further provides a memory reading method. Referring to the flowchart of FIG. 7, the embodiment of the present invention is as follows. (A) One address signal of the decode memory element is completely stored Until
(B) sequentially receiving and storing a part of one address signal of the decode memory element (for example, dividing one 32-bit address signal into four times and transmitting serially 8 bits each time); Outputting the address signal to the decode memory at one time; (c) receiving and storing the data of the address indicated by the address signal at one time from the decode memory; and (d) completely storing the data of the address indicated by the address signal. Is output sequentially (for example, 16-bit data is serially divided into two and output eight bits each time).
It has steps.

It goes without saying that the operation of the flow shown in FIG. 7 can be better understood with reference to FIG.

The embodiment according to FIG. 6 also provides a memory writing method, in which (a) receiving part of the one address signal sequentially until the address signal is completely stored. (For example, a 32-bit one address signal is divided into four times and received in 8-bit units in series). (B) Until the data to be stored at the address indicated by the one address signal is completely stored,
A part of the data is sequentially received and stored from the outside (for example, 16
Bit data is divided into two times and eight bits are received in series each time), and (c) writing data corresponding to the one address signal into the decode memory element at one time.

Referring to the embodiment of FIG. 6, it is obvious that the operation of the flow shown in FIG. 8 can be well understood.

[0041]

According to the present invention, the two signals WR ↓ and RD ↓ are given to control the timing of writing the address signal and the timing of reading the data, respectively, so that the peripheral control circuit is changed based on the actual address, and timely. Since the timing for writing the address signal and the timing for reading the data can be adjusted, the following excellent operational effects can be obtained.

After the data of one set of address signals is completely read, the address counter is automatically incremented,
Indicates the address of the next decode memory element. Therefore,
If the data to be read by the external peripheral controller is continuous address data, the external peripheral controller reads RD ↓ after the data indicated by the first set of addresses is read.
Can be used repeatedly to read the data indicated by these consecutive addresses directly, and there is no need to write subsequent address signals again. In this way, a large amount of address writing time can be saved.

Each time one address signal is completely written, WR ↓ becomes HIGH. At this time, the address pointer generator is cleared to 0 by the control circuit. On the other hand, after the data indicated by one address signal is read, R
D ↓ becomes HIGH, and the data pointer generator is cleared to 0 by the control circuit. Therefore, when there is a difference only in the low bit of the address signal input from the controller outside the IC, the different low bit input by the external controller is used as the low bit position (address pointer generator) of the address counter. Has already been cleared to 0). At this time, since the address present in the address counter indicates the desired next address, there is no need to write the invariable high bit of the address signal again. If RD ↓ is LOW by an external controller, the address is read. Since the operation can be started immediately, the access speed of the memory data can be improved.

[0044]

As can be seen from the above description, the apparatus and method of the present invention effectively modifies the advantages of serial and parallel arrangements, requiring the interface circuit to meet the actual required reading speed requirements. Since the number of pins can be adjusted, selectivity is greatly improved.

As described above, if only relatively low bits between each address signal change, data can be read by writing the changed address bits, and the data reading speed can be effectively reduced. Can be improved.

Further, as described above, when reading the data indicated by the continuous address signal, the operation of writing these continuous addresses can be omitted, and the data reading speed can be effectively improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a preferred embodiment of a memory read interface circuit according to the present invention.

FIG. 2 shows the timing of signals at each pin of the circuit of FIG.

FIG. 3 shows signal timing of each interface pin when eight address / data pins are provided in the circuit of FIG. 1;

FIG. 4 shows signal timing of each interface pin when four address / data pins are provided in the circuit of FIG. 1;

FIG. 5 shows signal timing of each interface pin when one address / data pin is provided in the circuit of FIG. 1;

FIG. 6 is a block diagram of a preferred embodiment of a memory access interface circuit according to the present invention.

FIG. 7 is a flowchart of a memory reading method according to the present invention.

FIG. 8 is a flowchart of a memory writing method according to the present invention.

FIG. 9 is a block diagram of a conventional circuit for reading memory data in a serial manner.

10 shows the timing of the signals at the interface pins of the circuit of FIG. 9;

FIG. 11 is a block diagram of a conventional circuit for reading memory data in a parallel manner.

FIG. 12 shows the timing of signals at interface pins of the circuit of FIG. 11;

[Explanation of symbols]

 6, 25 Interface circuit 7, 16 Control circuit 8, 17 Address storage circuit 9, 18 Bit selection circuit 10, 19 Data output buffer circuit 11, 20 Decode memory element 12, 22 Address pointer generator 13, 21 Address counter 14 One-way Data buffer 23 Two-way data buffer 15, 24 Data pointer generator

Claims (10)

(57) [Claims] 1. An interface circuit for reading data of a decode memory element having a plurality of addresses, each address corresponding to one data, wherein the decode memory is serially input from the outside several times. An address storage circuit for storing one address signal of an element and outputting the address signal to the decode memory element at the same time; and data for temporarily storing data of the decode memory element stored at an address indicated by the address signal An output buffer circuit, a bit selection circuit connected to the address storage circuit and the data output buffer circuit, the bit selection circuit setting the number of bits that the address storage circuit can receive simultaneously and the number of bits that the data output buffer circuit can output simultaneously Connected to the address storage circuit and the data output buffer circuit. Is the enable signal input to the address memory circuit and the data output buffer circuit, and a control circuit for outputting a write signal input to the decoding memory device, a plurality of address / data pins one Is the address and
And an external controller for dividing and transferring data.
Connected to the plurality of address / data pins.
Some numbers correspond to the bits set by the bit selection circuit.
A memory read interface circuit, which is determined according to the number of memory read interfaces. 2. The decoding memory device according to claim 1, wherein the decoding memory device is a read-only storage device, the address storage circuit is connected to the control circuit and the decoding memory device, and stores an address counter for storing the address signal; The address counter is connected to the control circuit, and generates a plurality of address pointer signals based on the number of bits set in the bit selection circuit. 2. The memory read interface circuit according to claim 1, further comprising an address pointer generator for providing a pointer signal, said address counter being an address pointer necessary for storing said address. 3. The data output buffer circuit is connected to the control circuit and the decode memory element, stores data stored at an address in the decode memory element indicated by the address signal, and stores the data several times. A one-way data buffer that divides and outputs serially; a plurality of data outputs that are connected to the bit selection circuit, the data buffer, and the control circuit, and that are based on the number of bits set in the bit selection circuit. A data pointer generator that determines a data bit to be output by the data buffer based on the plurality of data output pointers by generating a pointer. 3. The memory read interface circuit of claim 2, wherein: 4. The number of bits of an address received by the address storage circuit at one time is smaller than the number of bits of an address of the decode memory element, and the number of bits of data output at one time by the data output buffer circuit is the number of bits of the decode data. 2. The memory read interface circuit according to claim 1, wherein the number of bits of data stored in each address of the memory element is smaller than the number of bits. 5. An interface circuit for accessing data of a decode memory device having two states of reading and writing, wherein said interface circuit is configured to receive data from said decode memory device which is serially input from the outside several times. An address storage circuit for storing an address signal and outputting the address signal to the decode memory element at the same time; and a data of the decode memory element stored at an address indicated by the address signal when the interface circuit is in a reading state. Temporarily, and when the interface circuit is in the write state, a data buffer circuit for temporarily storing data input from the outside, and the address storage circuit and the data buffer circuit are connected to the data buffer circuit, The number of bits that the storage circuit can receive at the same time; A bit selection circuit for setting the number of bits that can be output simultaneously by the data buffer circuit; and an enabling signal connected to the address storage circuit and the data buffer circuit and input to the address storage circuit and the data buffer circuit. A control circuit for outputting a read / write signal input to the decode memory element and generating a signal for controlling the interface circuit, wherein a part of a plurality of address / data pins is
And an external controller for dividing and transferring data.
Connected to the plurality of address / data pins.
Some numbers correspond to the bits set by the bit selection circuit.
A memory access interface circuit, which is determined according to the number of memory accesses. 6. The decoding memory element is a random access memory element, the address storage circuit is connected to the control circuit and the decoding memory element, and stores an address counter for storing the address signal; A plurality of address pointer signals are generated based on the number of bits set in the bit selection circuit connected to the address counter and the control circuit, and each time an address signal of the decode memory element is input from outside, the address is generated. 6. An interface circuit for memory access according to claim 5, further comprising an address pointer generator for providing a pointer signal, said address counter being an address pointer necessary for storing said address. 7. The data buffer circuit is connected to the control circuit and the decode memory element, and is stored at an address in the decode memory element indicated by the address signal when the interface circuit is in a reading state. The data is stored at a time, the data is output serially in several divided steps, and conversely, when the interface circuit is in the write state,
A two-way data buffer that temporarily stores data input from the outside several times and writes the data to an address in the decode memory element indicated by the address signal; A data output pointer signal connected to the bit selection circuit, the two-way data buffer, and the control circuit, based on the number of bits set in the bit selection circuit;
6. A memory access as claimed in claim 5, further comprising a data pointer generator for determining the output / input data bits to be output each time by said two-way data buffer by providing it to the directional data buffer. Interface circuit. 8. The number of bits of an address received by the address storage circuit at one time is smaller than the number of bits of an address of each of the decode memory elements, and the number of data bits input / output by the data buffer at a time is equal to the number of bits of the decode. 6. The memory access interface circuit according to claim 5, wherein the number of bits of data corresponding to each address of the memory element is smaller than the number of bits. 9. A method for reading data stored in a decode memory element, wherein a part of a plurality of address / data pins includes an address and a data.
Data to an external controller for splitting and transferring data
Connected, the portion of the plurality of address / data pins
According to the number of bits set by the bit selection circuit.
Determining by Flip until said one address signal decoding memory element is completely stored, the method comprising: sequentially receiving stores some of the address signal from the outside, the address signal to the decoding memory element and transmitting at a time, receiving store data at the address indicated by the address signal at a time from the decode <br/> de memory device, until the data of the address which the address signal indicates is completely output, Sequentially outputting a part of the data to the outside. 10. A method for writing data to a decode memory element, wherein a part of a plurality of address / data pins includes an address and a data.
Data to an external controller for splitting and transferring data
Connected, the portion of the plurality of address / data pins
According to the number of bits set by the bit selection circuit.
And sequentially receiving and storing a part of the address signal from the outside until the signal for one address of the decode memory element is completely stored; and storing the address signal in the address indicated by the address signal. Until the data to be completely stored, sequentially receiving and storing a part of the data from the outside, and writing data at once to an address in the decode memory element indicated by the address signal. The write method of the decode memory element to be executed.