JPH05298179A - Memory control system - Google Patents

Abstract

PURPOSE:To obtain a memory control system where a bus master is capable of performing the write by a byte unit for a share memory by a transaction. CONSTITUTION:A bus master 11 generates a virtual address which a virtual base address is added to a normal address in an address conversion part 16 in order to perform a byte write, transmits it to an address bus 14b of a bus 14, adds a write mark to write data including data to be written by a byte unit in a data conversion part 17 and transmits it to a data bus 14a of the bus 14. A shared memory 15 which received the virtual address from an address conversion part 16, the write mark and write data from a data conversion part 17 modifies the data by a byte unit shown by the write mark of the read data at the inside of the shared memory 15 by the data by a byte unit shown by the write mark of the write data from the data conversion part 17 and this modified data is written.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control system having a plurality of bus masters and a shared memory shared by the plurality of bus masters. The present invention relates to a memory control system that can perform byte-wise writing (byte writing) when accessing.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a conventional memory control system having a plurality of bus masters and a shared memory. In FIG. 5, (1) to (3) are bus masters,
(4) is connected to these bus masters and has a predetermined byte width. (5) is connected to this bus and is shared by the above bus masters (1) to (3) with a memory having an ECC (error correction function). The shared memory is accessed in the unit of the data code width that is the same as the bus width.

Next, in the memory control system configured as described above, when the bus master (1) writes data (byte write) in 1-byte units to the shared memory (5) by a test and set command. The operation will be described. The data in byte units means data of 1 byte or more and less than the byte of the bus width. First, since the bus master (1) may access data from other bus masters (2) (3), these bus masters (2)
Exclusive control (bus lock) is performed for (3).

After that, the bus master (1) reads (reads data) the shared memory (5) with the same data width as the bus width based on the address for writing. Next, the bus master (1) modifies (changes) the byte-unit data of the address to be written (written) to the data having the same data width as the bus width read from the shared memory (5), and this modification is performed. Write to the shared memory with the same width as the bus width based on the address for writing the data. After writing,
The bus master (1) releases the bus lock with respect to the other bus masters (2) and (3), and the bus master (1) finishes writing the byte unit data to the shared memory (5) (byte write).

In short, in the above-mentioned conventional memory control system, when each bus master writes data in byte units (byte write) to the shared memory, other bus masters are bus-locked and then the shared memory is read. And the transaction of writing to the shared memory.

[0006]

As described above, in the conventional memory control system, when a bus master writes data in bytes in the shared memory, another bus master is bus-locked and two transactions are executed. It had to be done inseparably, and the process became complicated.

The present invention has been made in view of the above points, and an object of the present invention is to obtain a memory control system in which a bus master can write a byte unit into a shared memory by one transaction.

[0008]

A memory control system according to the present invention includes a plurality of bus masters and a bus connected to the plurality of bus masters and having a predetermined byte width.
It has a shared memory that is connected to this bus, is accessed by the bus master, and is shared by multiple bus masters that read and write data with the same width as the bus width.
It has an address conversion means for converting an address from a regular access address to a virtual address, and a data conversion means for adding data indicating a byte to be changed.

[0009]

According to the present invention, the address conversion means of the bus master informs that writing is performed in byte units by the address conversion from the regular access address to the virtual address, and the data conversion means of the bus master informs the data to be changed. ..

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows a configuration diagram. In FIG. 1, (11) to (13) are bus masters which are CPU masters whose details are shown in FIG. 2, and (14) is connected to these bus masters and has a predetermined byte width. A bus having a data bus, an address bus, and a control bus having a bus width of 2 to the nth power byte (n ≧ 1), and a bus width of 4 bytes in this embodiment. (15) is a shared memory shown in FIG. 3 which is connected to this bus and includes a memory with ECC shared by the bus masters (1) to (3). The unit of the data code width is the same as the bus width. In this embodiment, it is accessed by 4 bytes.

FIG. 2 is a configuration diagram showing the bus masters (11) to (13). In FIG. 2, (16) is a byte-unit write (byte write), so that the normal access address is changed to the virtual address. An address conversion unit for performing address conversion, for example, conversion into a virtual address (A + b) by adding a virtual base address b to the regular access address A, is connected to the address bus (14b) of the bus (14),
The virtual address (A + b) is sent to this address bus (14b).

(17) is a data conversion means for adding data indicating a byte to be changed, which is a data bus (14a) of the bus (14).
Connected to, for example, a data mark indicating a byte to be changed in the first data section, that is, a write mark WM indicating a byte of data to be written (byte write) in byte units of the data of the bus width is added. For converting the write data D including the data to be written in byte units to the burst data transfer, and for transmitting the write mark WM and the write data D to the data bus (14a). Is. (18) controls the address conversion means (16) and the data conversion unit (17), is connected to the control bus (14c) of the bus (14), and controls the shared memory (15) on the control bus (14c). It is a processor unit that sends out signals.

FIG. 3 is a block diagram of the shared memory (15). In FIG. 3, (19) is a bus master (20) via an address signal line (20) connected to the address bus (14b) of the bus (14). 11) ~
The virtual address is input from the address conversion unit (16) of (13), and the bus masters (11) to (13) are supplied via the control signal line (21) connected to the control bus (14c) of the bus (14). ), The control signal from the processor unit (18) is input, and the decoder unit that controls the address and timing is activated by the input control signal and is based on the virtual address input to the memory control line (22). Address signal (normal access address signal), a write mark enable signal is sent to the write mark enable line (23), and a byte write data signal is sent to the byte write data control line (24).

Reference numeral (25) is a data array section composed of a RAM for storing data, which is to be read and written by an address signal from the decoder section (19) inputted through the memory control line (22). The address of a copy (memory cell) is specified, and 3 bytes of 4-byte data having the same bus width as the bus width read from the storage unit of the specified address are stored.
It is transmitted via the two data lines (26),
Same as bus width input via data line (26) 4
The byte data is written in the storage unit at the specified address. (27) is the data bus (14a) of the bus (14)
Bus master (11) which is connected to the write mark enable line (23) and is input via the data bus (14a) by the write mark enable signal input via the write mark enable line (23). The write mark register unit holds the write mark WM sent from the data conversion units (13) to (13) and transmits the held write mark WM through the write mark data line (28).

Reference numeral (29) holds the read data of 4 bytes read from the data array section (25) inputted through the data line (26) and inputted through the byte write data control line (24). According to the byte write data signal from the decoder unit (19), the write mark WM held in the write mark register unit is read and held via the write mark data line (28), and the data array unit is read according to the write mark WM. The read data from (25) and the byte data from the data conversion unit (17) of the bus masters (11) to (13) input via the data bus (14a) of the bus (14) and 32 data lines In the data control unit that creates the data of the bus width by combining the write data including the data for writing,
In this embodiment, the 1-byte unit data indicated by the write mark in the read data having a bus width of 4 bytes read from the data array section (25) is transferred to the data bus (14a) of the bus (14) and The 1-byte unit indicated by the write mark of the second 4-byte data of the data cycle of the data from the data conversion unit (17) of the bus masters (11) to (13) input via the data line (30) The data is modified (changed), and the modified 4-byte data is transferred to the data array section (25) through the data line (26).

Reference numeral (31) is an error correction unit for performing error correction by the ECC, which is connected to the data line (30) and reads the read data read from the data array unit (25) into the data control unit.
When the data is held in (29), error correction is performed if necessary according to the check bit signal in the check bit signal line (32) connected to the data array section (25).

The decoder unit (19), the write mark register unit (27) and the data control unit (29) are connected to the bus master (11)-
Virtual address (A +) from the address conversion unit (16) of (13)
b) and the additional data (write mark WM) from the data conversion unit (17) constitute a means for realizing writing (byte write) in byte units in one bus cycle, More specifically, based on the virtual address (A + b) from the address conversion unit (16) of the bus masters (11) to (13), the data array unit (25 ) From the data conversion unit (17) of the bus master (11) to (13) after holding the read data in the holding unit that holds the read data and the read data. A means for storing and holding which byte is changed based on the above, a combination of the data (write data) from the data conversion unit (17) of the bus masters (11) to (13) and the read data held in the holding means hand Generating data-width, those constituting the means for writing the created data the data array (25).

Next, in the memory control system configured as described above, the operation when the bus master (11) writes 1-byte data (byte write) to the shared memory (15) will be described. In this embodiment, as shown in the timing chart of FIG. 4, although the bus width is 4 bytes and 16-byte data write is performed, a case where byte write is performed will be described. In FIG. 4, 16 bytes of data writing timing is shown in the upper part of the drawing, and byte-wise data writing (byte writing) timing is shown in the lower part of the drawing, t is a 16-byte write cycle, and a is an address. Cycle, d is a data cycle, A is a normal address, D _{1 to} D ₄ are data, A + b is a virtual address obtained by adding a virtual base address b to the normal access address A processed in the address cycle a, and WM is an address cycle a. A write mark composed of 4-byte data at the beginning of the subsequent data cycle d, and D is write data composed of 4-byte data including data to be written in byte units following the write mark WM.

Now, when the bus master (11) attempts to write data (byte write) in byte units, the bus master (11) sends a control signal from the processor section (18) to the bus (14).
To the control bus (14c) of the processor, and under the control of the processor unit (18), a virtual address obtained by adding the virtual base address b to the normal address A for byte writing in the address conversion unit (16) ( A + b) is generated and this virtual address (A
+ B) is sent to the address bus (14b) of the bus (14) in the address cycle a of a 16-byte write transaction, and the data conversion unit (17) includes data to be written in byte units for byte writing. A write mark WM is added to the write data D, the write mark WM is set at the beginning of the data cycle, the write data D is set next to the write mark WM of the data cycle, and then the data bus (1) of the bus (14).
4a).

The coder unit (19) of the shared memory (15) is a bus
The address conversion unit of the bus master (11) is activated by the control signal input through the control bus (14c) of (14) and is activated in the address cycle a through the address bus (14b) of the bus (14).
Input the virtual address (A + b) from (16). The decoder unit (19), to which the virtual address (A + b) is input, determines that the data is written in bytes (byte write) by accessing the virtual base address b, and after the address cycle a, that is, the data cycle d. The write mark enable signal is sent to the write mark register section (27) via the write mark enable line (23) when the first 4 bytes of the bus width of the data comes, and the write mark register section (27) receives the data. It is activated during the first 4-byte data transmission period of cycle d.

Then, the write mark register section (27)
Light mark WM sent from the data conversion unit (17) of the bus master (11) via the data bus (14a) of the bus (14)
Is input and the light mark WM is held. This light mark WM is the light mark register section (2
During the period written in (7), the decoder section (19) is connected to the bus (14).
Bus master (1
Virtual address (A + b) from the address converter (16) in 1)
The normal access address A before conversion, which is accessed by the bus master (11), is sent to the data array section (25) via the memory control line (22).

In the data array section (25) which receives the regular access address A, 4-byte data having the bus width selected by the regular access address A is transferred to the data line (2
The read data of 6 bytes is held in the buffer of the data control unit (29). At this time, if the read data from the data array section (25) is necessary,
After the error is corrected by the error correction unit (31), it is held in the buffer of the data control unit (29).

The 4-byte data transmission period of the second bus width in the data cycle d, that is, the write mark WM
When entering the period for sending the write data D including the data to be written in byte units sent next to,
The decoder section (19) sends a byte write data signal to the data control section (29) via the byte write data control line (24).

The data control unit (29) receiving the byte write data signal, the data to be written in byte units from the data conversion unit (17) of the bus master (11) via the data bus (14a) of the bus (14). While inputting 4-byte write data D including the read mark WM stored in the write mark register unit (27), the regular address A from the data array unit (25) previously stored in the buffer unit is read. Of the read data having a bus width of 4 bytes based on the data, the 1 byte unit data indicated by the write mark WM is transferred to the bus
Bus master (11) input via the data bus (14a) of
Write data D of 4 bytes from the data conversion unit (17)
One byte unit data indicated by the write mark WM among them, that is, data to be written in byte units is modified (changed) to generate four bytes of changed data.

The modified 4-byte modified data is sent to the data array section (25) through the data line (26), and the 4-byte data is stored in the data array section (25) at the address position of the normal access address A. Bytes of modified data are written. In this way, the bus master (11)
The write transaction for writing data in bytes (byte write) to the shared memory (15) ends.
In addition, 1 from the bus master (12) (13) to the shared memory (15)
The writing of data in byte units (byte writing) is also performed in the same manner.

In the memory control system configured as described above, the address conversion units of the bus masters (11)-(13)
By (16), the regular access address A is converted into a virtual address (A + b) to indicate that the data is written in byte units (byte write), and the bus master (11) to
Since the write mark WM added by the data conversion unit (17) of (13) indicates the byte unit data to be written in the write data D, the virtual address (A + b), the write mark WM and the write data D are received. The shared memory (15) is changed into the change data consisting of bytes of the bus width including the data in byte units to be written, and the data is written by one transaction, and it can be written to other bus masters. On the other hand, there is no need to lock the bus.

[0027]

As described above, according to the present invention, a plurality of bus masters, a bus having a predetermined byte width connected to the plurality of bus masters, and a bus connected to this bus,
An address conversion unit that includes a shared memory shared by a plurality of bus masters that is accessed from the bus master and that reads and writes data with the same width as the bus width, and that converts the bus master from a regular access address to a virtual address. Since the data conversion means for adding the data indicating the byte to be changed is included, the bus master can write data in byte units to the shared memory by one transaction.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 shows a bus master (11) in one embodiment of the present invention.
The block diagram which shows (13).

FIG. 3 is a configuration diagram showing a shared memory (15) in one embodiment of the present invention.

FIG. 4 is a timing chart showing a byte write transaction according to an embodiment of the present invention.

FIG. 5 is a configuration diagram showing a conventional memory control system.

[Explanation of symbols]

 11 bus master 12 bus master 13 bus master 14 bus 15 shared memory 16 address converter 17 data converter

Claims (1)

[Claims] 1. A plurality of bus masters, a bus having a predetermined byte width connected to the plurality of bus masters, connected to the bus, and accessed by the bus master,
A shared memory that is shared by the plurality of bus masters that read and write data with the same width as the bus width is provided, and the bus master performs address conversion means that performs address conversion from a regular access address to a virtual address, and performs a change. A memory control system comprising: data conversion means for adding data indicating a byte.