JPS5936773B2 - Local burst transfer control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a local burst transfer control method, and in particular, when transferring the first few bytes, data is transferred up to a word boundary to reduce the number of accesses to memory and improve data transfer efficiency. Related to local burst transfer control method.

Data transfer methods between input/output devices and memory include (1)
) The burst transfer method has a data buffer on the input/output device side and continuously transfers data to memory, and (
2) a byte multiplex transfer method that transfers one byte at a time from an input/output device; and (3) a fixed number of bytes at a time (generally a fixed number of bytes, 4 bytes, 6 bytes, etc. depending on the input/output device). There is a local burst transfer method that transfers the number of bytes (specified as 8 bytes) and transfers the several bytes multiple times.

(1) above is used when a specific input/output device transfers data to the memory continuously, so very long data is transferred in a short period of time. Since a specific input/output device exclusively uses the memory, access requests from other input/output devices are temporarily suppressed.

Therefore, as described in (2) above, data is transferred one byte at a time, and necessary data is sequentially transferred to multiple input/output devices in a time-sharing manner. Since only one byte is transferred, data transfer takes a long time. Therefore, as an intermediate method of (1) and (2) above, there is the local burst transfer method of (3) above, but this also has the following problems. For example, as shown in FIG. 1A, the word W. There is a request to transfer 13 bytes of data from byte position 2 of word W3 to byte position 2 of word W3, and if this is to be transferred, for example, 4 bytes at a time,
Because of the word boundaries, in order to read bytes 1, 2, 3, and 4, which are the first transferred data, the channel first reads word Wo from the memory, and then Retain bytes 1 and 2 and then read word W1 back into memory to retrieve bytes 3 and 4. In this way, the required bytes 1 to 4 are sent out. Then, on the next data transfer, the channel again reads word W1 to the memory and retrieves bytes 5 and 6, reads word W2 and retrieves bytes 7 and 8, and sends out the required bytes 5-8. In this way, the channel accesses the memory twice each time it transfers data, so in order to transfer the necessary bytes 1 to [phase], the channel has to read the same word multiple times. Become. Therefore, the local burst transfer method has a problem in that the data transfer speed becomes slow depending on the byte address of the required byte due to word boundaries.
Therefore, in order to improve such problems, the present invention has the following objectives:
When transferring the first few bytes of data, we use a local burst transfer control method that sends the bytes up to the word boundary, even if the data does not reach 4 bytes, so that the next data transfer can be sent word by word. To this end, the local burst transfer control method of the present invention is equipped with a memory, a channel, and an input/output device that can be accessed in word units, and handles multiple byte access requests in response to memory access requests. In a local burst transfer method that transfers data multiple times, data address setting means sets the byte position of the data address, address updating means changes the data address according to the data transfer, and word boundary setting means sets the byte position of the data address. A word boundary detection means for detecting a word boundary and a control means for controlling data transfer are provided, and when a byte transfer is performed up to a word boundary, the word boundary detection means detects this, and the control means temporarily stops the subsequent data transfer. The next data transfer is performed from the first byte of the word.

An embodiment of the present invention will be described below based on FIG. 2 and with reference to FIG. 1.

FIG. 2 shows the configuration of an embodiment of the present invention.

In the figure, 1 is the main memory, 2 is the main memory data register, 3 is the data address buffer, 4 is the counter,
5 is a decoder, 6 is a control circuit, 7 is a data transfer control circuit, 8-0 to 8-3 are data buffer registers, G
O to Gll are gates.

The main memory 1 stores data necessary for data processing, and is used to send out read-requested data in response to read/write requests from input/output devices 1/0, and to respond to write requests. is used to write data.

The main memory data register 2 temporarily holds data read from the main memory 1 or temporarily sets data to be written to the main memory 1.

The data address buffer 3 sets the byte position of the data to be transferred.
The lower two bits of the CCW data address are set.

4 is a +1 counter which increments the value of the data address buffer 3 by 1 every time 1 bit of data is transferred.

The decoder 5 decodes the value set in the data address buffer 3 and generates necessary control signals.

The control circuit 6 performs various controls based on data retest from the input/output device 1/O, temporarily stops data transfer, etc. It performs control for accessing the memory 1 and reading and writing necessary data from the main memory 1.

The data transfer control circuit 7 performs various controls when reading data from or writing data from the main memory 1.

Data buffer registers 8-0 to 8-3 (registers in which read/write data is set,
When reading data from main memory 1, the data set in main memory data register 2 is transmitted one byte at a time, and when writing data to main memory 1, the data set in main memory data register 2 is transmitted one byte at a time. The set data is sequentially sent to the main memory data register.

Now, when a request is made to transfer bytes 1 to ◎ from the input/output device 1/0 as shown in FIG. 1, the data transfer control circuit 7 first sends a data request signal REQ,
The start address and the number of transferred bytes are transmitted to the channel control circuit 6.

As a result, the channel accesses main memory 1, but at this time, data address buffer 3 is
The lower two bits of the data address are set from the start address of CW. As a result, the byte position "10" of byte 1 in Figure 1A is set.The channel first reads the necessary byte 1 from the data buffer register 8-3 of the input/output device 1/O, and Set to the byte position indicated by data address buffer 3 in data register 2.

Then, the data address barometer 3 is incremented by +1 step. As a result, data address buffer 3 becomes “11”.
], and gate G3 is turned on. In input/output device 1/0, data buffer registers 8-0 to 8-3 become 1 because 1 byte of data is read by the channel.
Byte shifted and byte 2 goes into 8-3. The channel then reads this byte 2 and is set to byte 3 where gate G3 of main memory data register 2 is on. Then, data address buffer 3 is incremented by 1.
At this time, the decoder 5 detects that the word boundary has been crossed by changing from "11" to "00", and the control circuit 6 is notified. and data transfer is paused,
The channel stores bytes 2 and 3 of main memory data register 2 in main memory 1. Thereafter, the 1/O sets bytes 3 to 6 of the next word in data buffer registers 8-0 to 8-3, and turns on the data request signal REQ. When the channel sees that the data request signal REQ from the input/output device is turned on, it performs the next data transfer. At this time, the channel reads the necessary byte 3 from the data buffer register 8-3 of /O,
Since the byte position of main memory data register 2 indicated by data address buffer 3 is "00", it is set to byte 0. Continuing, part-time jobs 4 and 5
, 6 in main memory data register 2. At this time, data address buffer 3 changes from "11" to "0".
0'', the decoder 5 detects that the word boundary has been crossed, notifies the control circuit 6 of a data transfer temporary stop signal, and transfers the contents of the main memory data register 2 to word W1 of the main memory 1. Store. Furthermore, during the next data transfer, the channel can sequentially transfer bytes 7, 8, 9, [phase], and finally transfer bytes (0), @, [phase] required by word W3. Can be transferred.

In this way, from word W1 onwards, by accessing one word, data of four bytes, which is the maximum number of bytes to be transferred, can be continuously transferred. In addition, in the case of a write operation, the channel first fetches one word from memory at the starting address, and then fetches the first byte position (CC
From the data address of W (the specified byte address) to the buffer registers 8-0, 8-1, etc. of the input/output device
・Written to.

The input/output device shifts the data by 1 byte each time data is written from the channel to buffer registers 8-0, 8-1, etc. to create an empty byte position in data buffer register 8-0. to make. And Ward W.
The first 2 bytes of data buffer register 8-2
, 8-1. At this time, data address buffer 3 becomes "11", and decoder 5 transmits a transfer stop signal to control circuit 6. As a result, the control circuit 6 controls the data transfer control circuit 7 to transfer the data buffer.
The data in registers 8-1 and 8-2 are taken into /O to create free space in data buffer registers 8-0 to 8-3. Thus, the next time you transfer data,
It becomes possible to transfer to the input/output device 1/O from the first byte position of the word. As explained above, according to the present invention, when accessing memory, it is possible to first control the transfer of the amount of bytes up to the word boundary. As a result, memory access can be performed very efficiently. In the above description, the number of bytes in one transfer is 4 bytes, but the present invention is of course not limited to this.

For example, when the number of bytes transferred in one transfer is 8 bytes, it is sufficient to set the lower 3 bits of the data address in the data address buffer and use 8 data buffer registers.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of data transfer, and FIG. 2 is a configuration diagram of an embodiment of the present invention. In the figure, 1 is the main memory, 2 is the main memory data register, 3 is the data address buffer, 4 is the counter,
5 is a decoder, 6 is a control circuit, 7 is a data transfer control circuit, 8-0 to 8-3 are data buffer registers, G
O to Gll indicate gates, respectively.

Claims (1)

[Claims] 1 In the local burst transfer method, which is equipped with memory, channels, and input/output devices that can be accessed in word units, and which transfers multiple bytes of data multiple times in response to memory access requests, the byte position of the data address is set. data address setting means for
Address updating means for changing a data address according to data transfer, word boundary detection means for detecting a word boundary, and control means for controlling data transfer are provided, and when a byte transfer is performed up to a word boundary, the above word boundary is detected. A local burst transfer control method characterized in that the detection means detects this and the control means temporarily stops subsequent data transfer, and the next data transfer is performed from the first byte of a word. .