JP2905041B2 - Message transceiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a message transmitting / receiving apparatus in a multiprocessor system.

[0002]

2. Description of the Related Art FIG.
FIG. 7 is a block diagram showing a conventional message transmitting / receiving apparatus shown in the specification and the drawings attached to No. 281, and FIG. 6 is a block diagram showing a multiprocessor system using the present invention and the conventional message transmitting / receiving apparatus. . In FIG. 6, reference numeral 1 denotes a processor A for transmitting a message, reference numeral 2 denotes a processor B having the same hardware as that of the processor A1 and receiving a message, and reference numeral 3 denotes a processor for receiving the processor A1 and the processor B2. This is the system bus to be connected. In the processor A1, reference numeral 4 denotes a transmission task for executing a transmission operation in a message transfer by software, reference numeral 5 denotes a port A used on the transmission side in the message transfer, and reference numeral 6 denotes a port used in the message transfer on the transmission side. Current address A. Similarly, in the processor B2, reference numeral 7 denotes a reception control unit which executes a transmission operation in a message transfer by hardware, 8 denotes a port B used on the reception side in the message transfer, and 9 denotes a reception side in the message transfer. Is the current address B used in the.

Next, in FIG. 7, 2 is a processor B,
Reference numeral 7 denotes a reception control unit, which is denoted by the same reference numeral in FIG. Reference numeral 10 denotes a received message flowing on the system bus 3 not shown in FIG. 7, and includes, for example, a memory including a packet ID, a source address, a destination address, a type, a port ID, a current address, and memory access information. This is 32-byte information necessary for access.

A reception first-in first-out memory (hereinafter referred to as reception FI) 11 is a reception memory for receiving and buffering the reception message 10.
FO). In the information output from the reception FIFO 11, reference numeral 20 denotes a port ID which is one of information in the reception message 10, reference numeral 21 denotes a current address, and reference numeral 22 denotes memory access information (for example, address, data, command, etc.). It is. Note that port ID2
0 is information corresponding to the port B8, and a current address 21 is a lower address of a memory block of a reception buffer described later.
If it is KB, the range of the address value is from 000H to ff
fH.

Reference numeral 12 denotes a rewritable base address register for storing a base address 23, and reference numeral 13 denotes a base address 2 from the base address register 12.
3 is a port address generation unit that adds the port ID 20 from the reception FIFO 11 and generates a port address 24. Reference numeral 14 denotes a port designation address storage table for storing the port designation address 25 as data. Reference numeral 15 denotes a buffer address 2 obtained by adding the port designation address 25 from the port designation address storage table 14 and the current address 21 from the reception FIFO 11.
6 is a buffer address generating unit for generating the address No. 6. 16 is a buffer address 26 from the buffer address generator 15
Memory access information 2 from the reception FIFO 11 according to
2 is a reception buffer for storing the number 2.

Here, the base address 23 is a leading physical address of the port designation address storage table 14, and the port address 24 is a physical address of the port designation address storage table 14. Port designation address 2
Reference numeral 5 denotes a head physical address of a memory block in the reception buffer 16 corresponding to the port, and a buffer address 26 is a physical address of a memory block of the reception buffer 16 in which the memory access information 21 is stored.

The reception control unit 7 extracts the port ID 20, the current address 21, and the memory access information 22 from the reception FIFO 11 and executes various reception operations.

Next, the operation will be described. Message transfer between processors in a multiprocessor system is usually performed via a port. Here, the received message 10 when the processor A1 accesses the processor B2 has, for example, a size of 32 bytes, a packet ID, a type, a source address, a destination address, a current address 21, and a port ID2.
Information such as 0, memory access information 22, etc. is allocated to a specific location. Here, in FIG. 6, when the processor A1 transfers a message using the ports A5 and B8 to the processor B2, the reception control unit 7 receives the reception message 10 in the reception FIFO 11 and then controls the reception. A reception process until the unit 7 stores the memory access information 22 in the reception buffer 16 will be described.

[0009] In the processor A1, the received message 1 transmitted to the processor B2 using the port A5.
0 is received by the reception FIFO 11 in the processor B2. Now, the base address 23 in the base address register 12 (hereinafter referred to as “30000
H) is set in advance, and the port designation address 25 (hereinafter, “46000H” is added to 30,000H, 30
“47000H” to 001H and “41000” to 30002H
000H "is stored in advance), the reception control unit 7 first selects the memory block of the reception buffer 16 in which the memory access information 22 is to be set.
0 (hereinafter the port ID is described as "2H") and the current address 21 (hereinafter the current address is described as "770H") are transmitted. In the port address generation unit 13, the port ID 20 (2H) and the base address 23 (30000)
H) plus the port address 24 (30000H + 2
H = 30002H).

[0010] From the port designation address storage table 14 receiving the port address 24, a port designation address 25 (41000H) which is data corresponding to the port address 24 (30002H) is output to the buffer address generator 15. (Memory block 2 is selected). The buffer address generation unit 15
The current address 21 (770
H) and the port designation address 25 (41000H) output from the port designation address storage table 14, and the buffer address 26 (41000H + 770H =
41770H) and outputs it to the reception buffer 16. In the reception buffer 16, the memory access information 22 output from the reception FIFO 11 is stored in the buffer address 26 (41770) from the buffer address generation unit 15.
H) is stored in a memory block (memory block 2).

[0011]

Since the conventional message transmitting / receiving apparatus is configured as described above, when receiving the same port ID, the previous transfer number is stored and set in a predetermined transfer area. It takes time to start the transfer on the transmitting side, and when the transfer amount increases, data is written to the designated area of another port ID, and the data transferred by the other port ID is destroyed. In addition to the danger, when the central processing unit (hereinafter referred to as CPU) of the receiving processor reads data sent from the transmitting processor, the base address register 1
The information in the base address 23 and the port designation address storage table 14 set to 2 must be calculated to determine the address of the reception buffer 16, and there is a problem that it takes a long time to read data. .

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and the speed of the message transmission / reception operation and the speed of the CPU read operation of the reception data can be increased. It is an object of the present invention to obtain a message transmitting / receiving device that can reliably protect the message.

[0013]

According to a first aspect of the present invention, there is provided a message transmitting / receiving apparatus for counting the number of memory access information stored in a receiving buffer for each port ID output from a receiving memory. An address counting unit, and a current address generating unit that generates a pseudo current address by multiplying the count value of the current address counting unit by the number of bytes of the memory access information,
The buffer address generation unit adds the pseudo current address output from the current address generation unit to the port designation address output from the port designation address storage table to generate a buffer address.

According to a second aspect of the present invention, there is provided a message transmission / reception apparatus, comprising: a memory block maximum area table for storing a memory block maximum area indicating a storage capacity of each memory block of a reception buffer according to a port address; An overrun check section is provided for generating an overrun error signal indicating that the buffer address has exceeded the maximum memory block area based on a comparison between the block maximum area and the pseudo current address output from the current address generation section.

According to a third aspect of the present invention, there is provided a message transmitting / receiving apparatus, wherein an adding register storing an added address, and a base address from a base address register when an overrun error signal is insignificant, and when a significant value is significant. In addition, a base address conversion unit is provided for adding the added address thereto and inputting it to the port address generation unit.

According to a fourth aspect of the present invention, there is provided a message transmitting / receiving apparatus, wherein a port ID register in which a port ID of a memory block to be read is set, and a port ID register in response to a write / read select signal of a receiving buffer. And the port ID sent by the receiving memory
And a port ID selector for sending to the port address generator and the current address counter, and one of a relative address and a pseudo current address of necessary information by the select signal, and sending them to the buffer address generator. A current address selector is provided.

In the message transmitting / receiving apparatus according to the fifth aspect of the present invention, the information necessary for the port ID selector is stored in the port ID selector.
Is input instead of the port ID from the port ID register, and the port ID selector selects one of the upper address and the port ID from the receiving memory by a select signal. Is sent to the port address generator and the current address counter.

[0018]

According to the first aspect of the present invention, the buffer address generation unit adds the number of bytes of the memory access information to the number of memory access information stored in the reception buffer counted for each port ID output from the reception memory. By adding the pseudo current address obtained by the multiplication and the port designation address output from the port designation address storage table to generate a buffer address, the setting of the current address in the received message becomes unnecessary.

The overrun check unit according to the second aspect of the present invention compares the maximum memory block area stored in the maximum memory block area table according to the port address with the pseudo current address output from the current address generation unit. By generating an overrun error signal indicating that the buffer address has exceeded the maximum area of the memory block, it is possible to prevent the storage contents of the memory block of another port ID from being destroyed.

In the base address converter according to the third aspect of the invention, the base address from the base address register is stored as it is when the overrun error signal is insignificant, and is stored in the addition register when the overrun error signal is significant. By adding the added address and inputting it to the port address generation unit, the transfer of data over the area is guaranteed.

The port ID selector according to the fourth aspect of the present invention may be configured so that one of the port ID set in the port ID register and the port ID transmitted by the receiving memory is used.
The data is selected by the write / read select signal of the receive buffer and sent to the port address generator and the current address counter. The current address selector determines the relative address of the necessary information on the receive buffer and the pseudo current from the current address generator. By selecting one of the addresses by the select signal and sending it to the buffer address generator, it is not necessary to calculate the access address from the contents of the port designation address storage table for data reading.

Further, the port ID selector according to the invention described in claim 5 is arranged so that the port I
D, one of the upper address specifying the port ID of the memory block in which the necessary information is stored and the port ID from the receiving memory are selected by a select signal, and the current address is set to the port address generator. By transmitting the data to the address counting unit, the port ID register is deleted, and the process of setting the port ID in the port ID register becomes unnecessary.

[0023]

【Example】

Embodiment 1 FIG. Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the first aspect of the present invention. In the figure, 2 is a processor B, 12
Is a base address register, 13 is a port address generation unit, 14 is a port designation address storage table, 15 is a buffer address generation unit, 16 is a reception buffer, 20 is a port ID, 21 is a current address, 22 is memory access information, and 23 is A base address, 24 is a port address, 25 is a port designation address, and 26 is a buffer address, which are the same as or equivalent to those in the related art denoted by the same reference numerals in FIG. Reference numeral 10 denotes a received message different from the conventional message having the same reference numeral in FIG. 7 in that the current address 21 is not included, and reference numeral 11 denotes a conventional message having the same reference numeral shown in FIG. 7 is different from the conventional FIFO having the same reference numeral in FIG. 7 in that it extracts the port ID 20 and the memory access information 22 from the reception FIFO 11 and executes various reception operations. This is a different reception control unit.

Reference numeral 30 denotes a count signal output by the reception control unit 7 for notifying that the reception message 10 has been received by the reception FIFO 11. Reference numeral 31 denotes a counter provided for each port ID 20. When the count signal 30 is received from the control unit 7, the reception FIFO 11
Counts up the counter corresponding to the port ID 20 received from the CPU, outputs a count value as a result thereof, and displays a CPU (not shown) of the processor B2.
Is a current address count section that is held until reading of the count value is completed. Reference numeral 32 denotes a count value corresponding to the port ID 20 output from the current address count unit 31 and the reception buffer 16 from the reception FIFO 11.
Is a current address generation unit that multiplies the number of bytes of the memory access information 22 sent to the buffer address generation unit 15 by multiplying the result by the pseudo current address 33 to the buffer address generation unit 15. The pseudo current address 33 is the same as the conventional current address indicated by reference numeral 21 in FIG. 7, but is generated and output by the current address generation unit 32, and the 1
It is not the current address contained in 0.

Next, the operation will be described. First, the received message 10 when the processor A1 accesses the processor B2 has, for example, a size of 32 bytes, a packet ID, a type, a source address, a destination address, and a port ID 2 as in the conventional case.
Information such as 0, memory access information 22, etc. is allocated to a specific location. Here, in FIG. 6, the processor A1 may, port A5, by using the port B8, when performing the current address A6 and current address B 9 is a message transfer does not use the processor B4, receiver control unit 7 receives A reception process from when the reception message 10 is received by the FIFO 11 to when the reception control unit 7 stores the memory access information 22 in the reception buffer 16 will be described.

In the processor A1, the received message 1 transmitted to the processor B2 is transmitted using the port A5.
0 is received by the reception FIFO 11 in the processor B2. When the reception FIFO 11 receives the reception message 10, the reception control unit 7 generates a count signal 30 and transmits it to the current address count unit 31. When receiving the count signal 30, the current address counting unit 31 counts up the counter corresponding to the port ID 20 in the received message 10, and the resulting count value (here, described as “4H”) is the current address. Output to the generation unit 32. In the current address generation unit 32, the input count value (4H) and the FIFO
The number of bytes of the memory access information 22 stored in the reception buffer 16 from O11 (here, 4K bytes, “10
00H ”), and the resulting pseudo current address 33 (1000H × 4 = 4000)
H) is generated and output to the buffer address generator 15.

Now, as in the conventional case, the base address 23 (“30000”) is stored in the base address register 12.
H ") and the port designation address 25 (" 410 ") in" 30002H "of the port designation address storage table 14.
00H ”) is stored in advance, the port designation address 25 (41000H) is stored in the buffer address generation unit 15 from the port designation address storage table 14 by the same processing (port ID 20,“ 2H ”) as in the conventional case. The buffer address generation unit 1
5 is a pseudo current address 33 (“4000H”) output from the current address generation unit 32 and a port designation address 25 from the port designation address storage table 14.
(41000H) and add the buffer address 26 (4
(1000H + 4000H = 45000H) and outputs it to the reception buffer 16. In the reception buffer 16, the memory access information 22 output from the reception FIFO 11
Is stored in the memory block (memory block 2) indicated by the buffer address 26 (45000H) from the buffer address generation unit 15.

As a result, the processor A1 on the transmitting side does not need to set the current address 21 in the received message 10, and accordingly, the time for generating a message at the time of transmission is shortened, and the speed of message transmission / reception can be increased.

Embodiment 2 FIG. Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram showing one embodiment of the invention described in claim 2, and the corresponding parts are denoted by the same reference numerals as in FIG. 1 and the description thereof is omitted. In the figure, 40 indicates the maximum number of bytes that can be stored in the corresponding memory block of the reception buffer 16. The memory block maximum area corresponding to the port specification address 25 in the port specification address storage table 14 is a memory block maximum area table in which the port address 24 from the port address generation unit 13 is stored as a physical address. Reference numeral 41 compares the memory block maximum area output from the memory block maximum area table 40 with the pseudo current address 33 from the current address generator 32, and the buffer address 26 output from the buffer address generator 15 exceeds the memory block maximum area. An overrun check unit 42 checks whether or not the buffer address 26 has exceeded the maximum area of the memory block. An overrun error signal 42 is output from the overrun check unit 41 to the reception control unit 7 when it detects that the buffer address 26 has exceeded the maximum memory block area. is there.

Next, the operation will be described. Here, as in the case of the first embodiment, in FIG.
Performs the message transfer using the port A5 and the port B8 to the processor B2.
The reception processing from reception of the reception message 10 to the reception FIFO 11 until the reception control unit 7 stores the memory access information 22 in the reception buffer 16 will be described. In addition,
Here, the port designation address 25 (also in the first embodiment)
Described as “41000H” as in the case of
And the pseudo current address 33 (again, "45000
H ”) is the same as that in the first embodiment, and the description thereof is omitted.

Assume that the maximum memory block area ("3000H") is stored in advance in the area indicated by the port address 24 (30002H) in the memory block maximum area table 40. The reception control unit 7 refers to the memory block maximum area table 40 and performs the same processing as in the first embodiment (the port ID 20 is “2H”), and the port address 24 (3000) output by the port address generation unit 13.
2H) memory block maximum area (3000)
H) is output to the overrun check unit 41. here,
The overrun check unit 41 includes the current address generation unit 32 together with the maximum memory block area (3000H).
The pseudo current address 33 (4000H) is also input, and the two are compared. As a result of the comparison, when the pseudo current address 33 is larger than the memory block maximum area, the overrun error signal 42 sent to the reception control unit 7 becomes significant, and the pseudo current address 33 is smaller than the memory block maximum area. If it is, it becomes insignificant.

Accordingly, when the pseudo current address 33 (4000H) is equal to or larger than the maximum memory block area (3000H) as in the above example, the overrun error signal 42 input to the reception control unit 7 becomes significant. ,
The reception control unit 7, which recognizes that the overrun has occurred, stops the reception signal after the output of the buffer address 26 by the buffer address generation unit 15, and then notifies the reception side or the transmission side processor of the occurrence of the error. . On the other hand, the input overrun error signal 42
If the request is invalid, the reception control unit 7 executes the same processing as in the first embodiment, and stores the memory access information 22 from the reception FIFO 11 in the reception buffer 16.

Embodiment 3 FIG. Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram showing one embodiment of the invention described in claim 3, and the corresponding parts are denoted by the same reference numerals as in FIG. 2 and description thereof is omitted. In the figure, reference numeral 50 denotes an addition register which can be set by the CPU of the processor B2 (not shown) and stores an addition address (here, described as "10000H") in the base address register 12. Reference numeral 51 denotes an addition address (10000H) output from the addition register 50 and a base address 23 (30000) output from the base address register 12 when the overrun error signal 42 output from the overrun check unit 41 becomes significant.
H) is added, and the resulting converted base address (40000H) is output.
Is insignificant, the base address conversion unit outputs the base address 23 as it is.

Next, the operation will be described. Here, as in the second embodiment, the processor A1 shown in FIG.
Performs the message transfer using the port A5 and the port B8 to the processor B2.
The reception processing from reception of the reception message 10 to the reception FIFO 11 until the reception control unit 7 stores the memory access information 22 in the reception buffer 16 will be described. In addition,
Here, when an overrun occurs, the overrun error signal 42 output by the overrun check unit 41 is output.
Is the same as that in the second embodiment, and a description thereof will be omitted. Note that the overrun signal 42 is
In the case of no intention, the base address conversion section 51 outputs the base address 23 as it is.

Here, in the memory area indicated by the port address 24 ("30002H") in the port designation address storage table 14 and the memory block maximum area table 40, a normal port designation address 25 (here, "410
00H ”) and the maximum area of the memory block (here,“ 30
00H ”) and the port address 24 (here,“ 30002H + 1 ”) to which the content of the addition register 50 has been added.
0000H = 40002H "),
Port designation address 2 to store the remainder during overrun
5 (here, “53000H”) and the maximum memory block area (here, “4000H”) are stored in advance.

The reception control unit 7 stores the memory access information 22 in the reception buffer 16 by the same processing as in the first embodiment while the overrun error signal 42 being received is insignificant. On the other hand, the received overrun error signal 4
When 2 becomes significant, the reception control unit 7 recognizes that an overrun has occurred, and temporarily stops the reception processing after the output of the buffer address 26. At that time, the base address conversion unit 51 adds the added address (10000H) output from the addition register 50 to the base address 23 (30000H) from the base address register 12 to generate a converted base address (40000H). Is output to the port address generation unit 13. The port address generator 13 converts the converted base address (4000
0H) to the port ID 20 (2
H) is added to generate a port address 24 (40002H). The port address 24 (40002H) is sent to the port designation address storage table 14, from which the changed port designation address 25 (53000H) is output to the buffer address generation unit 15.

As a result, the reception processing after the output of the buffer address 26 that has been temporarily stopped is restarted, and the buffer address generation unit 15 sends the port designation address 25
(53000H) and the pseudo current address 33 (4000H) from the current address generator 32 are added, and the generated buffer address 26 (53000H + 4000) is obtained.
H = 57000H) to the reception buffer 16. In the reception buffer 16 receiving the data, the memory access information 22 output from the reception FIFO 11 is stored in the memory block indicated by the buffer address 26 (57000H).

Embodiment 4 FIG. Next, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a block diagram showing one embodiment of the invention described in claim 4, and the corresponding parts are denoted by the same reference numerals as in FIG. 1 and description thereof is omitted. In the figure, reference numeral 61 denotes a CPU which controls the operation of the processor B2;
Reference numeral 63 denotes a CPU access control unit for controlling the access of the CPU 61 to the reception buffer 16, and 63 arbitrates a request for accessing the reception buffer 16 from the CPU access control unit 62 and the reception control unit 7, and the arbitration result is obtained. Of the receiving buffer 16 as a select signal 67 for selecting writing / reading. 64
Is a current address selector for selecting one of a relative address (CPU address) 68 output from the CPU 61 and a pseudo current address 33 output from the current address generator 32 in accordance with a select signal 67 thereof. Reference numeral 65 denotes a port I in which the port ID of the memory block from which the reception buffer 16 is read is set as the port ID (CPU data) 69 by the CPU 61.
D port register 66 is the port ID register 65
And the port ID 2 output from the reception FIFO 11
0 is a port ID selector that selects one of 0 according to the select signal 67.

Next, the operation will be described. here,
The operation when the CPU 61 obtains the received memory access information from the reception buffer 16 will be described, and the operation of receiving from a port is the same as that in the first embodiment, and the description is omitted. When the CPU 61 acquires the memory access information in the reception buffer 16, the CPU 61
Reference numeral 61 indicates that the port ID of the memory block in which the required memory access information is stored must be set as CPU data 69 in the port ID register 65 in advance.

First, the CPU 61 stores the relative address of the required data (address from the head of the data group) in the CPU 61.
The CPU access control unit 62 is activated at the same time as outputting the address 68 to the current address selector 64.
The activated CPU access control unit 62 outputs an access request to the arbitration unit 63, and upon receiving the request, the arbitration unit 63 determines the access request from the reception control unit 5.
That is, if the access from the CPU 61 is possible, the select signal 67 is sent to the reading side of the reception buffer 16, that is, the CP.
Change to U access side. In response to the select signal 67, the port ID selector 66 makes the CPU 61
The port ID set in the D register 65 is output to the port address generator 13. Thereafter, the port designation address 25 corresponding to the port ID set in the port ID register 65 is input from the port designation address storage table 14 to the buffer address generation unit 15 along the same route as when data is received. On the other hand, in the current address selector 64, the CPU address 68 from the CPU 61 is selected by the select signal 67 from the arbitration unit 63, and is added to the port designation address 25 in the buffer address generation unit 15 to generate the buffer address 26. . As described above, any memory access information corresponding to the port ID set in the port ID register 65 can be read out from the reception buffer 16 simply by specifying a relative address.

Embodiment 5 FIG. Next, a fifth embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a block diagram showing one embodiment of the invention described in claim 5, and the corresponding parts are denoted by the same reference numerals as in FIG. 4 and description thereof is omitted. In the figure, 71 is C
The port I is output from the CPU 61 instead of the PU data 69, and is output from the port ID register 65 in the fourth embodiment.
This is an upper address directly input to the port ID selector 66 instead of D, and is a bit higher than the CPU address 68 which is also output from the CPU 61 and input to the current address selector 64. Port ID of the stored memory block
Is specified.

Next, the operation will be described. When the CPU access control unit 62 is activated, the CPU 61 outputs a relative address of required data to the current address selector 64 as a CPU address 68, and the port ID selector 66 stores the required data as an upper address. The port ID of the memory block being output is output. That is, the address to be accessed by the CPU 61 is a value obtained by shifting (multiplying) the port ID by the number of bits of the CPU address 68 and adding the relative address.
The CPU 61 divides and outputs such an address into the upper address 71 and the CPU address 68, so that the subsequent processing is the same as that described in the fourth embodiment, and obtains necessary data from the reception buffer 16. Can be.

[0043]

As described above, according to the first aspect of the present invention, the current address count for counting the number of memory access information stored in the reception buffer for each port ID output from the reception memory. And a current address generating unit for generating a pseudo current address by multiplying the counted value by the number of bytes of the memory access information, and storing the previous transfer count of each port ID. , Even if there is no information of the current address, the divided message with the same port ID can be stored in the reception buffer.
There is an effect that a message transmission / reception device that can reduce the generation time of a message at the time of transmission and can further speed up the operation of transmitting / receiving a message can be obtained.

According to the second aspect of the present invention, when a transfer exceeding the area of each port ID set in the memory block maximum area table occurs, the storage in the reception buffer is stopped. Therefore, even if the transfer amount becomes enormous and an overrun occurs, it is possible to prevent the storage contents of the other port ID areas from being destroyed, and to transmit and receive a message with higher reliability. effective.

According to the third aspect of the invention, when an overrun occurs, the port address input to the port designation address storage table is forcibly changed to exceed the port ID area. Since the transfer is transferred to an area that does not overlap with other port IDs, the receiving operation can be continued even if an overrun occurs, and the transfer of data over the area is guaranteed. There is an effect that can be.

According to the fourth aspect of the present invention, C
At the time of PU access, the current address selector
CPU address from U to the port ID selector
Since U is configured to select the port ID set in the port ID register, it is not necessary to calculate the access address from the contents of the port designation address storage table each time data is read from the reception buffer, and the data is stored in the reception buffer. This has the effect of speeding up the acquisition of memory access information.

According to the fifth aspect of the present invention, the upper address designating the port ID of the memory block in which the necessary information is stored is directly input to the port ID selector. There is no need to set a port ID in the port ID register, so that the setting process becomes unnecessary, and the port ID register can be deleted.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a message transmitting / receiving apparatus according to Embodiment 1 of the present invention.

FIG. 2 is a block diagram showing a message transmitting / receiving apparatus according to Embodiment 2 of the present invention.

FIG. 3 is a block diagram showing a message transmitting / receiving apparatus according to Embodiment 3 of the present invention.

FIG. 4 is a block diagram showing a message transmitting / receiving apparatus according to Embodiment 4 of the present invention.

FIG. 5 is a block diagram showing a message transmitting / receiving apparatus according to Embodiment 5 of the present invention.

FIG. 6 is a block diagram showing a multiprocessor system in which the present invention and a conventional message transmitting / receiving apparatus are used.

FIG. 7 is a block diagram showing a conventional message transmitting / receiving device.

[Explanation of symbols]

 7 Reception control unit 10 Reception message 11 Reception memory (reception FIFO) 12 Base address register 13 Port address generation unit 14 Port designation address storage table 15 Buffer address generation unit 16 Reception buffer 20 Port ID 22 Memory access information 23 Base address 24 Port address 25 Port designation address 26 Buffer address 31 Current address count unit 32 Current address generation unit 33 Pseudo current address 40 Memory block maximum area table 41 Overrun check unit 42 Overrun error signal 50 Addition register 51 Base address conversion unit 64 Current address selector 65 Port ID Register 66 Port ID selector 67 Select signal 68 Relative address (CPU address) 69 Port ID (CPU data) 71 Upper address

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. ⁶ , DB name) G06F 13/00 G06F 15/163

Claims (5)

(57) [Claims] 1. A receiving memory of a first-in first-out type for receiving a received message, a receiving control unit for controlling a receiving operation by extracting a port ID and memory access information from the receiving memory, and a receiving control unit for controlling a receiving operation. A reception buffer storing the memory access information, a port designation address storage table storing a port designation address indicating a memory block of the reception buffer, and a base address which is a leading physical address value of the port designation address storage table. And the base address read from the base address register is added to the port ID output from the reception memory to generate a port address input to the port designation address storage table. port An address generation unit, a current address count unit that counts the number of memory access information stored in the reception buffer for each port ID output from the reception memory, A current address generation unit that generates a pseudo current address by multiplying the number of bytes of the access information; and a port specification address output from the port specification address storage table and the pseudo current address output from the current address generation unit. And a buffer address generation unit for generating a buffer address of the reception buffer. 2. A memory block maximum area table storing a memory block maximum area indicating a storage capacity of each memory block of the reception buffer in an area indicated by the port address, and a memory from the memory block maximum area table. A block maximum area is compared with a pseudo current address from the current address generation section to check whether a buffer address output from the buffer address generation section exceeds the memory block maximum area and generate an overrun error signal. The message transmission / reception device according to claim 1, further comprising an overrun check unit that performs the operation. 3. An addition register for storing an additional address to be added to the base address when the buffer address exceeds the maximum area of the memory block, and an overrun error signal output from the overrun check unit is insignificant. A base address conversion unit that adds the base address from the base address register as it is, and adds the base address to the base address if significant, and inputs the base address to the port address generation unit. The message transmitting / receiving device according to claim 2, wherein 4. A port ID register in which a port ID of a memory block from which the reception buffer is read is set, and one of a port ID from the reception memory and a port ID from the port ID register is stored in the reception buffer. A port ID selector for selecting according to a select signal for selecting writing / reading of data and sending it to the port address generation unit and the current address counting unit; a relative address of necessary information on the reception buffer; 2. The message transmitting / receiving apparatus according to claim 1, further comprising: a current address selector for selecting one of the pseudo current addresses according to the select signal and sending the selected pseudo current address to the buffer address generator. 5. Selecting one of an upper address indicating a port ID of a memory block from which reading of the reception buffer is performed and a port ID from the reception memory in accordance with a select signal for selecting writing / reading of the reception buffer; A port ID selector for sending to the port address generation unit and the current address count unit, and selecting one of a relative address of necessary information on the reception buffer and a pseudo current address from the current address generation unit according to the select signal; 2. The message transmitting / receiving apparatus according to claim 1, further comprising a current address selector for sending to the buffer address generating unit.