JPH0721102A - Message transmitter/receiver - Google Patents

Abstract

PURPOSE:To store divided messages of the same port ID in a receiving buffer, to shorten the generation time of the messages at the time of transmission, and to speed up transmitting and receiving operation for the messages by storing the last number of transferred messages of each port ID. CONSTITUTION:This device is provided with a current address count part 31 which counts how many pieces of memory access information 22 are stored in the receiving buffer 16 by port IDs 20 outputted from a receiving memory 11 and a current address generation part 32 which multiplies the calculated value of this current address count part 31 by the number of bytes of the memory access information 22 to generate a dummy current address 33. Then a buffer address generation part 15 adds the dummy current address 33 outputted from this current address generation part 32 to a port specification address 25 outputted from a port specification address storage table 14 to generate a buffer address 26. Consequently, the need to set the current address in a received message 10 is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a message transmitting / receiving device in a multiprocessor system.

[0002]

2. Description of the Related Art FIG. 7 shows, for example, 1992 Japanese Patent Application No. 114.
FIG. 7 is a block diagram showing a conventional message transmitting / receiving apparatus shown in the specification and drawings attached to No. 281, and FIG. 6 is a block diagram showing a multiprocessor system in which the present invention and the conventional message transmitting / receiving apparatus are used. . In FIG. 6, 1 is a processor A that transmits a message, 2 is a processor B that has the same hardware as this processor A1 and that receives a message, and 3 is a processor A1 and a processor B2. The system bus to connect to. Further, in the processor A1, 4 is a send task for executing a send operation in message transfer by software, 5 is a port A used on the sender side in the message transfer, and 6 is also used on the sender side in the message transfer. Current address A. Similarly, in the processor B2, 7 is a reception control unit that executes a transmission operation in message transfer by hardware, 8 is a port B used on the receiving side in message transfer, and 9 is a receiving side in message transfer. It is the current address B used in.

Next, in FIG. 7, 2 is a processor B,
Reference numeral 7 denotes a reception controller, which is shown in FIG. 6 with the same reference numerals. Reference numeral 10 denotes a received message that flows on the system bus 3 (not shown in FIG. 7), and includes, for example, a memory including a packet ID, a source address, a destination address, a type, a port ID, a current address, memory access information, and the like. This is 32 bytes of information required for access.

Reference numeral 11 is a reception first-in first-out memory (hereinafter referred to as reception FI) as a reception memory for receiving and buffering the reception message 10.
FO). In the information output from the reception FIFO 11, 20 is a port ID which is one of the information in the reception message 10, 21 is also a current address, and 22 is also memory access information (for example, address, data, command, etc.). Is. In addition, port ID2
0 is the information corresponding to the port B8, the current address 21 is the lower address of the memory block of the receive buffer described later, for example, the memory capacity of one port is 4
If it is KB, the range of the address value is 000H to ff
fH.

Reference numeral 12 is a rewritable base address register for storing a base address 23, and 13 is a base address 2 from the base address register 12.
3 is a port address generation unit for generating a port address 24 by adding 3 and the port ID 20 from the reception FIFO 11. 14 is a port designation address storage table for storing the port designation address 25 as data, and 15 is a buffer address 2 obtained by adding the port designation address 25 from the port designation address storage table 14 and the current address 21 from the reception FIFO 11.
6 is a buffer address generation unit for generating 6. 16 is a buffer address 26 from the buffer address generator 15
Memory access information 2 from the receiving FIFO 11 according to
It is a reception buffer for storing 2.

The base address 23 is the head physical address of the port designation address storage table 14, and the port address 24 is the physical address of the port designation address storage table 14. Port designated address 2
Reference numeral 5 is the head physical address of the memory block in the reception buffer 16 corresponding to the port, and buffer address 26 is the physical address of the memory block of the reception buffer 16 in which the memory access information 21 is stored.

The reception control unit 7 extracts the port ID 20, the current address 21, and the memory access information 22 from the reception FIFO 11 and executes various reception operations.

Next, the operation will be described. Message transfer between processors in a multiprocessor system is typically done through ports. Here, the received message 10 when the processor A1 accesses the processor B2 has, for example, a size of 32 bytes, a packet ID, a type, a source address, a destination address, a current address 21, and a port ID2.
Information such as 0 and memory access information 22 is assigned to a specific location. Here, in FIG. 6, when the processor A1 transfers a message using the port A5 and the port B8 to the processor B2, the reception control unit 7 receives the reception message 10 in the reception FIFO 11, and then the reception control is performed. A reception process until the unit 7 stores the memory access information 22 in the reception buffer 16 will be described.

In the processor A1, the received message 1 sent to the processor B2 using the port A5
0 is received by the reception FIFO 11 in the processor B2. Now, the base address 23 in the base address register 12 (hereinafter, the base address is "30000
H ”is described in advance, and the port designation address 25 in the port designation address storage table 14 (hereinafter,“ 46000H ”is set to 30000H, 30
"47000H" for 001H and "41" for 30002H
000H "is stored in advance, the reception controller 7 first selects the memory block of the reception buffer 16 in which the memory access information 22 is set.
0 (hereinafter, port ID is described as “2H”) is transmitted, and current address 21 (hereinafter, current address is described as “770H”) is transmitted. In the port address generation unit 13, the port ID 20 (2H) and the base address 23 (30000)
Port address 24 (30000H + 2)
H = 30002H) is output.

From the port designation address storage table 14 that has received the port address 24, the port designation address 25 (41000H), which is the data corresponding to the port address 24 (30002H), is output to the buffer address generation unit 15. (Memory block 2 is selected). The buffer address generator 15 receives the received F
The current address 21 (770
H) and the port designation address 25 (41000H) output by the port designation address storage table 14 are added to obtain the buffer address 26 (41000H + 770H =
41770H) is generated and output to the reception buffer 16. In the reception buffer 16, the memory access information 22 output from the reception FIFO 11 is the buffer address 26 (41770) from the buffer address generation unit 15.
H) is stored in the memory block (memory block 2).

[0011]

Since the conventional message transmitting / receiving apparatus is constructed as described above, when the same port ID is received, the previous transfer number is stored and set in a predetermined transfer area. However, if it takes time to start the transfer on the transmission side, and if the transfer amount increases, the data is written to the designated area of the other port ID, and the data transferred by the other port ID is destroyed. Not only is there a risk, but when the central processing unit (hereinafter referred to as CPU) of the receiving side processor reads the data sent from the transmitting side processor, the base address register 1
The information in the base address 12 and the port designation address storage table 14 set to 2 must be calculated to determine the address of the reception buffer 16, which causes a problem that it takes a long time to read the data. .

The present invention has been made in order to solve the above-mentioned problems, and speeds up the message transmission / reception operation and the CPU read operation of the received data, so that the transfer data can be transferred at any transfer amount. It is an object of the present invention to provide a message transmitting / receiving device capable of surely protecting a message.

[0013]

According to a first aspect of the present invention, there is provided a message transmitting / receiving apparatus, wherein the number of stored memory access information stored in a receiving buffer is counted for each port ID output from the receiving memory. An address count unit and a current address generation unit that generates a pseudo current address by multiplying the count value of the current address count unit by the number of bytes of memory access information are provided.
The buffer address generation unit adds the pseudo current address output from the current address generation unit to the port designation address output from the port designation address storage table to generate the buffer address.

According to a second aspect of the present invention, there is provided a message transmission / reception apparatus which stores a memory block maximum area indicating a storage capacity of each memory block of a reception buffer in accordance with a port address, and a memory thereof. An overrun check unit is provided for generating an overrun error signal indicating that the buffer address has exceeded the memory block maximum area based on the comparison between the block maximum area and the pseudo current address output from the current address generation section.

Further, in the message transmitting / receiving apparatus according to the present invention as defined in claim 3, the base address from the base register from which the base address from the base register is unchanged when the adder register storing the adder address and the overrun error signal is insignificant, and when it is significant. A base address conversion unit for adding the added address to it and inputting it to the port address generation unit is provided.

According to a fourth aspect of the present invention, there is provided a message transmission / reception apparatus, wherein a port ID register in which a port ID of a memory block to be read is set, and a port buffer ID register by a write / read select signal of a reception buffer. And the port ID sent by the receiving memory
Port ID selector for sending to the port address generating unit and the current address counting unit, and one of relative address and pseudo current address of necessary information by the select signal and sending to the buffer address generating unit. It is provided with a current address selector.

Further, in the message transmitting / receiving apparatus according to the present invention as defined in claim 5, in the port ID selector, an upper address for designating a port ID of a memory block in which necessary information is stored is set as a port ID from the port ID register. Instead, the port ID selector selects one of the upper address and the port ID from the receiving memory by the select signal and sends it to the port address generating unit and the current address counting unit.

[0018]

According to the first aspect of the present invention, in the buffer address generation unit, the number of bytes of the memory access information is added to the storage number of the memory access information stored in the reception buffer counted for each port ID output from the reception memory. The pseudo current address obtained by the multiplication and the port designation address output from the port designation address storage table are added to generate a buffer address, thereby making it unnecessary to set the current address in the received message.

The overrun check unit in the invention according to claim 2 compares the memory block maximum area stored in the memory block maximum area table according to the port address with the pseudo current address output from the current address generation unit. By generating an overrun error signal indicating that the buffer address has exceeded the maximum area of the memory block, it is possible to prevent the stored contents of the memory block having another port ID from being destroyed.

Further, in the base address conversion unit according to the third aspect of the present invention, when the overrun error signal is insignificant, the base address from the base address register is stored as it is, and when it is significant, it is stored in the addition register in the base address. By adding the added address and inputting it to the port address generation unit, the transfer of the data that has exceeded the area is guaranteed.

Further, the port ID selector in the invention according to claim 4 is arranged such that one of the port ID set in the port ID register and the port ID sent by the receiving memory is
It is selected by the write / read select signal of the receive buffer and sent to the port address generator and the current address count unit. The current address selector uses the relative address of the necessary information on the receive buffer and the pseudo current from the current address generator. By selecting one of the addresses with the select signal and sending it to the buffer address generation unit, it becomes unnecessary to calculate the access address from the contents of the port designation address storage table when reading data.

The port ID selector according to the invention of claim 5 is the port ID from the port ID register.
A select signal selects one of a higher-order address, which is input instead of D, of the port ID of the memory block in which the necessary information is stored and a port ID from the receiving memory, and selects the port address generator and the current address. By sending to the address count unit, the port ID register is deleted, and the process of setting the port ID in the port ID register becomes unnecessary.

[0023]

【Example】

Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the invention described in claim 1. In the figure, 2 is a processor B, 12
Is a base address register, 13 is a port address generation unit, 14 is a port designation address storage table, 15 is a buffer address generation unit, 16 is a reception buffer, 20 is a port ID, 21 is a current address, 22 is memory access information, and 23 is A base address, 24 is a port address, 25 is a port designation address, and 26 is a buffer address, which are the same as or equivalent to those of the conventional one denoted by the same reference numeral in FIG. Note that 10 is a received message different from the conventional message which is assigned the same reference numeral in FIG. 7 in that it does not include the current address 21, and 11 is conventional which is assigned the same reference numeral in FIG. 7 in that the current address 21 is not output. 7 is a receiving FIFO different from that shown in FIG. 7, and 7 is different from the conventional receiving FIFO in that the port ID 20 and the memory access information 22 are extracted from the receiving FIFO 11 and various receiving operations are executed. They are different reception control units.

Reference numeral 30 is a count signal output by the reception control unit 7 to notify the reception FIFO 11 that the reception message 10 has been received. Reference numeral 31 is provided with a counter for each port ID 20, When the count signal 30 from the control unit 7 is received, the reception FIFO 11
The counter corresponding to the port ID 20 received from the CPU counts up and outputs the count value as a result, and the processor B2 is not shown in the CPU.
Is a current address counting unit that holds the count value until the reading is completed. Reference numeral 32 denotes a count value corresponding to the port ID 20 output from the current address counting unit 31, and the reception buffer 16 from the reception FIFO 11.
Is a current address generation unit that multiplies the number of bytes of the memory access information 22 sent to, and outputs the result to the pseudo current address 33 and the buffer address generation unit 15. The pseudo current address 33 is an address similar to the conventional current address indicated by reference numeral 21 in FIG. 7, but is generated and output by the current address generation unit 32, and the received message is 1
It is not the current address contained in 0.

Next, the operation will be described. First, the received message 10 when the processor A1 accesses the processor B2 has, for example, a size of 32 bytes and packet ID, type, source address, destination address, port ID 2 as in the conventional case.
Information such as 0 and memory access information 22 is assigned to a specific location. Here, in FIG. 6, when the processor A1 uses the port A5 and the port B8 to perform message transfer to the processor B4 without using the current address A6 and the current address B6, the reception control unit 7 receives the reception FIFO 11 The reception process from the reception of the reception message 10 to the reception control unit 7 storing the memory access information 22 in the reception buffer 16 will be described.

In processor A1, received message 1 sent to processor B2 using port A5
0 is received by the reception FIFO 11 in the processor B2. When the reception FIFO 11 receives the reception message 10, the reception controller 7 generates a count signal 30 and transmits it to the current address count unit 31. When the current address counting unit 31 receives the count signal 30, the current address counting unit 31 counts up the counter corresponding to the port ID 20 in the received message 10, and the count value (described here as “4H”) is the current address. It is output to the generation unit 32. In the current address generation unit 32, the input count value (4H) and the FIF
The number of bytes of the memory access information 22 stored in the reception buffer 16 from O11 (here, 4 Kbytes, “10
00H ") and the resulting pseudo current address 33 (1000H × 4 = 4000).
H) is generated and output to the buffer address generation unit 15.

Now, as in the conventional case, the base address 23 ("30000") is stored in the base address register 12.
H ”) and the port designation address 25 (“ 410 ”) in“ 30002H ”of the port designation address storage table 14.
00H ") is stored in advance, the port designation address 25 (41000H) is stored in the buffer address generation unit 15 from the port designation address storage table 14 by the same process (port ID 20," 2H ") as in the conventional case. It is output to the buffer address generation unit 1
5 is a pseudo current address 33 (“4000H”) output from the current address generation unit 32 and a port designation address 25 from the port designation address storage table 14.
(41000H) is added to the buffer address 26 (4
1000H + 4000H = 45000H) is generated and output to the reception buffer 16. In the reception buffer 16, the memory access information 22 output from the reception FIFO 11
Is stored in the memory block (memory block 2) indicated by the buffer address 26 (45000H) from the buffer address generation unit 15.

As a result, the processor A1 on the transmission side does not need to set the current address 21 in the received message 10, and the message generation time at the time of transmission can be shortened accordingly, and the speed of message transmission / reception can be increased.

Example 2. Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram showing an embodiment of the invention described in claim 2. Corresponding parts are designated by the same reference numerals as those in FIG. 1 and their explanations are omitted. In the figure, 40 indicates the maximum number of bytes that can be stored in the corresponding memory block of the reception buffer 16. The memory block maximum area corresponding to the port specified address 25 of the port specified address storage table 14 on a one-to-one basis is the memory block maximum area table in which the port address 24 from the port address generation unit 13 is stored as a physical address. Reference numeral 41 compares the maximum memory block area output from the maximum memory block area table 40 with the pseudo current address 33 from the current address generation unit 32, and the buffer address 26 output from the buffer address generation unit 15 exceeds the maximum memory block area. An overrun check unit 42 for checking whether or not is an overrun error signal output from the overrun check unit 41 to the reception control unit 7 when it detects that the buffer address 26 exceeds the maximum memory block area. is there.

Next, the operation will be described. Here, as in the case of the first embodiment, in FIG.
When the message transfer using the port A5 and the port B8 is performed to the processor B2, the reception control unit 7
A description will be given of the reception processing from when the reception message is received by the reception FIFO 11 until the reception control unit 7 stores the memory access information 22 in the reception buffer 16. In addition,
Here, the port designation address 25 (also in the first embodiment
In the same way as the case of, describe as "41000H"),
And the pseudo current address 33 (also "45000
The reception processing up to the generation and output of (described as “H”) is the same as that of the first embodiment, and thus the description thereof is omitted.

It is assumed that the memory block maximum area ("3000H") is stored in advance in the area indicated by the port address 24 (30002H) in the memory block maximum area table 40. The reception control unit 7 refers to the memory block maximum area table 40, and performs the same process as in the first embodiment (port ID 20 is “2H”), and the port address 24 (3000) output by the port address generation unit 13 is output.
2H) memory block maximum area (3000
H) is output to the overrun check unit 41. here,
In the overrun check unit 41, the current address generation unit 32 as well as the memory block maximum area (3000H)
The pseudo current address 33 (4000H) is also input, and both are compared. As a result of the comparison, if the pseudo current address 33 is equal to or larger than the maximum memory block area, the overrun error signal 42 sent to the reception control unit 7 becomes significant, and the pseudo current address 33 is less than the maximum memory block area. If it is

Therefore, as in the above example, when the pseudo current address 33 (4000H) is equal to or larger than the maximum memory block area (3000H), the overrun error signal 42 input to the reception controller 7 becomes significant. ,
The reception control unit 7, which recognizes that the overrun has occurred, stops the reception signal after the output of the buffer address 26 by the buffer address generation unit 15 and then notifies the processor of the reception side or the transmission side of the occurrence of the error. . On the other hand, the input overrun error signal 42
If is insignificant, the reception control unit 7 executes the same processing as in the first embodiment, and stores the memory access information 22 from the reception FIFO 11 in the reception buffer 16.

Example 3. Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram showing an embodiment of the invention described in claim 3. Corresponding parts are designated by the same reference numerals as in FIG. 2 and their explanations are omitted. In the figure, reference numeral 50 is an addition register configured to be settable by the CPU of the processor B2 (not shown) and storing an addition address (described as "10000H" here) in the base address register 12. When the overrun error signal 42 output from the overrun check unit 41 becomes significant, 51 indicates an addition address (10000H) output from the addition register 50 and a base address 23 (30000) output from the base address register 12.
H) is added, the converted base address (40000H) resulting from the addition is output, and the overrun error signal 42
Is a base address conversion unit that outputs the base address 23 as it is.

Next, the operation will be described. Also here, as in the case of the second embodiment, in FIG.
When the message transfer using the port A5 and the port B8 is performed to the processor B2, the reception control unit 7
A description will be given of the reception processing from when the reception message is received by the reception FIFO 11 until the reception control unit 7 stores the memory access information 22 in the reception buffer 16. In addition,
Here, when an overrun occurs, the overrun error signal 42 output from the overrun check unit 41 is output.
Since the reception processing until it becomes significant is similar to that of the second embodiment, the description thereof will be omitted. At that time, the base address conversion unit 51 outputs the base address 23 as it is.

Here, in the memory area indicated by the port address 24 (“30002H”) of the port designation address storage table 14 and the memory block maximum area table 40, the normal port designation address 25 (here, “410”).
00H ”) and the memory block maximum area (here,“ 30H ”
00H ”) is added to the port address 24 (here,“ 30002H + 1 ”) to which the contents of the addition register 50 are added.
In the memory area indicated by 0000H = 40002H ″),
Port specification address 2 that should store the remainder when overrun
5 (here, “53000H”) and the memory block maximum area (here, “4000H”) are stored in advance.

The reception control section 7 stores the memory access information 22 in the reception buffer 16 by the same processing as in the first embodiment while the received overrun error signal 42 is insignificant. On the other hand, the received overrun error signal 4
When 2 becomes significant, the reception control unit 7 recognizes that an overrun has occurred and suspends the reception processing after the output of the buffer address 26. At that time, the base address conversion unit 51 adds the addition address (10000H) output from the addition register 50 to the base address 23 (30000H) from the base address register 12 to generate a converted base address (40000H), Is output to the port address generation unit 13. The port address generator 13 converts the converted base address (4000
0H) port ID 20 (2 from the reception FIFO 11)
H) is added to generate a port address 24 (40002H). The port address 24 (40002H) is sent to the port designation address storage table 14, and the changed port designation address 25 (53000H) is output from the port designation address storage table 14 to the buffer address generation unit 15.

As a result, the reception process after the output of the temporarily stopped buffer address 26 is resumed, and the buffer address generation unit 15 causes the port designated address 25
(53000H) and the pseudo current address 33 (4000H) from the current address generator 32 are added to generate the buffer address 26 (53000H + 4000).
H = 57000H) is sent to the reception buffer 16. In the reception buffer 16 that has received it, the memory access information 22 output from the reception FIFO 11 is stored in the memory block indicated by the buffer address 26 (57000H).

Example 4. Next, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a block diagram showing an embodiment of the invention described in claim 4. Corresponding parts are designated by the same reference numerals as those in FIG. 1 and their explanations are omitted. In the figure, 61 is a CPU that controls the arithmetic operation of the processor B2, and 62
Is a CPU access control unit that controls access of the CPU 61 to the reception buffer 16, and 63 arbitrates a request to access the reception buffer 16 from the CPU access control unit 62 and the reception control unit 7, and the arbitration result thereof. Is an arbitration unit that outputs as a select signal 67 for selecting writing / reading of the reception buffer 16. 64
Is a current address selector that selects one of the relative address (CPU address) 68 output from the CPU 61 and the pseudo current address 33 output from the current address generation unit 32 according to the select signal 67. Reference numeral 65 is a port I in which the port ID of the memory block from which the reception buffer 16 is read is set as the port ID (CPU data) 69 by the CPU 61.
D is a register, and 66 is the port ID register 65.
Contents and port ID2 output from the receive FIFO 11
The port ID selector selects one of 0 according to the select signal 67.

Next, the operation will be described. here,
The operation when the CPU 61 acquires the received memory access information from the reception buffer 16 will be described, and the reception operation from the port is the same as in the first embodiment, and therefore the description thereof is omitted. When the CPU 61 acquires the memory access information in the reception buffer 16, the CPU
Reference numeral 61 needs to previously set the port ID of the memory block in which the necessary memory access information is stored in the port ID register 65 as the CPU data 69.

The CPU 61 first determines the relative address of the required data (address from the beginning of the data group) by the CPU.
The address 68 is output to the current address selector 64, and at the same time, the CPU access control unit 62 is activated.
The activated CPU access control unit 62 outputs an access request to the arbitration unit 63, and the arbitration unit 63 which receives the arbitration unit arbitrates with the access request from the reception control unit 5.
That is, if access from the CPU 61 is possible, the select signal 67 is sent to the reading side of the reception buffer 16, that is, CP.
Change to U access side. By this select signal 67, the port ID selector 66 causes the CPU 61 to send the port I
The port ID set in the D register 65 is output to the port address generation unit 13. Thereafter, the port designation address 25 corresponding to the port ID set in the port ID register 65 is input from the port designation address storage table 14 to the buffer address generation unit 15 through the same route as when receiving data. On the other hand, in the current address selector 64, the CPU address 68 from the CPU 61 is selected by the select signal 67 from the arbitration unit 63, and is added to the above-mentioned port designation address 25 in the buffer address generation unit 15 to generate the buffer address 26. . As described above, any memory access information corresponding to the port ID set in the port ID register 65 can be read out from the reception buffer 16 only by designating the relative address.

Example 5. Next, a fifth embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a block diagram showing an embodiment of the invention described in claim 5. Corresponding parts are designated by the same reference numerals as those in FIG. 4 and their explanations are omitted. In the figure, 71 is C
Instead of the PU data 69, the data is output from the CPU 61, and the port I from the port ID register 65 in the fourth embodiment is output.
It is a higher-order address that is directly input to the port ID selector 66 instead of D, and is a higher-order bit than the CPU address 68 that is also output from the CPU 61 and is input to the current address selector 64. Port ID of the stored memory block
Is specified.

Next, the operation will be described. When the CPU access control unit 62 is activated, the CPU 61 outputs the relative address of the required data as the CPU address 68 to the current address selector 64, and at the same time, the required data is stored in the port ID selector 66 as the upper address. The port ID of the memory block that is being output is output. That is, the address accessed by the CPU 61 is a value obtained by shifting (multiplying) the port ID by the number of bits of the CPU address 68 and adding the relative address.
The CPU 61 divides such an address into the upper address 71 and the CPU address 68 and outputs the same, so that the subsequent processing is the same as that described in the fourth embodiment, and the necessary data is acquired from the reception buffer 16. You can

[0043]

As described above, according to the first aspect of the present invention, the current address count for counting the number of memory access information stored in the reception buffer for each port ID output from the reception memory. Section and a current address generation section for multiplying the count value by the number of bytes of the memory access information to generate a pseudo current address, and configured to store the previous transfer number of each port ID. Even if the information of the current address does not exist in, it becomes possible to store the divided message with the same port ID in the receiving buffer,
There is an effect that the message generation time at the time of transmission is reduced, and a message transmission / reception device capable of speeding up the message transmission / reception operation is obtained.

According to the second aspect of the invention, when the transfer exceeding the area of each port ID set in the memory block maximum area table occurs, the storage in the receiving buffer is stopped. Since it is configured as described above, it is possible to prevent the contents stored in the other port ID areas from being destroyed even when the amount of transfer becomes enormous and an overrun occurs, so that more reliable message transmission / reception can be performed. effective.

According to the third aspect of the invention, when an overrun occurs, the port address input to the port designation address storage table is forcibly changed so that the port ID area is exceeded. Since the transfer amount is configured to be transferred to the area that does not overlap with other port IDs, the receiving operation can be continued even if an overrun occurs, and the transfer of the data that has exceeded the area can be guaranteed. There is an effect that can be.

According to the invention described in claim 4, C
When PU is accessed, CP is added to the current address selector
CP of the CPU address from U to the port ID selector
Since U is configured to select the port ID set in the port ID register, it is not necessary to calculate the access address from the contents of the port designation address storage table when reading data from the reception buffer, and the data is stored in the reception buffer. This has the effect of speeding up acquisition of memory access information.

According to the fifth aspect of the present invention, the upper address for designating the port ID of the memory block in which the necessary information is stored is directly input to the port ID selector. Since there is no need to set the port ID in the port ID register, the setting process becomes unnecessary and the port ID register can be deleted.

[Brief description of drawings]

FIG. 1 is a block diagram showing a message transmitting / receiving apparatus according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a message transmitting / receiving apparatus according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a message transmitting / receiving apparatus according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a message transmitting / receiving apparatus according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a message transmitting / receiving apparatus according to a fifth embodiment of the present invention.

FIG. 6 is a block diagram showing a multiprocessor system in which the present invention and the conventional message transmitting / receiving apparatus are used.

FIG. 7 is a block diagram showing a conventional message transmitting / receiving apparatus.

[Explanation of symbols]

 7 reception control unit 10 reception message 11 reception memory (reception FIFO) 12 base address register 13 port address generation unit 14 port designation address storage table 15 buffer address generation unit 16 reception buffer 20 port ID 22 memory access information 23 base address 24 port address 25 Port designation address 26 Buffer address 31 Current address counting unit 32 Current address generation unit 33 Pseudo current address 40 Memory block maximum area table 41 Overrun check unit 42 Overrun error signal 50 Addition register 51 Base address conversion unit 64 Current address selector 65 Port ID Register 66 Port ID selector 67 Select signal 68 Relative address (CPU address) 69 Start ID (CPU data) 71 Upper address

Claims (5)

[Claims] 1. A first-in / first-out reception memory for receiving a reception message, a reception control unit for extracting a port ID and memory access information from the reception memory to control a reception operation, and a reception controller for extracting a reception operation from the reception memory. A reception buffer in which the memory access information is stored, a port designation address storage table in which a port designation address indicating a memory block of the reception buffer is stored, and a base address which is a top physical address value of the port designation address storage table Is added to the base address register for storing the port address, the port ID output from the reception memory and the base address read from the base address register are added to generate a port address input to the port designation address storage table. port An address generation unit, a current address counting unit that counts the number of stored memory access information stored in the reception buffer for each port ID output from the reception memory, and a count value of the current address counting unit in the memory. A current address generation unit that multiplies the number of bytes of access information to generate a pseudo current address, the port designation address output from the port designation address storage table, and the pseudo current address output from the current address generation unit. And a buffer address generation unit for generating a buffer address of the reception buffer. 2. A memory block maximum area table storing a memory block maximum area indicating a storage capacity of each memory block of the reception buffer in an area indicated by the port address, and a memory from the memory block maximum area table. A block maximum area is compared with a pseudo current address from the current address generation section to check whether the buffer address output from the buffer address generation section exceeds the memory block maximum area and generate an overrun error signal. The message transmitting / receiving apparatus according to claim 1, further comprising: 3. An addition register that stores an addition address to be added to the base address when the buffer address exceeds the maximum area of the memory block, and the overrun error signal output by the overrun check unit are insignificant. If it is significant, the base address from the base address register is used as it is, and if significant, the added address is added to the base address, and a base address conversion unit for inputting to the port address generation unit is provided. The message transmitting / receiving apparatus according to claim 2. 4. A port ID register in which a port ID of a memory block from which the reception buffer is read is set, and one of the port ID from the reception memory and the port ID from the port ID register are set in the reception buffer. , A port ID selector that selects according to a select signal that selects writing / reading, and sends to the port address generating unit and the current address counting unit, a relative address of necessary information on the receiving buffer, and the current address generating unit. 2. The message transmitting / receiving apparatus according to claim 1, further comprising a current address selector which selects one of the pseudo current addresses according to the select signal and sends the selected one to the buffer address generating unit. 5. One of an upper address indicating a port ID of a memory block from which the reception buffer is read and a port ID from the reception memory is selected according to a select signal for selecting writing / reading of the reception buffer, A port ID selector for sending to the port address generation unit and the current address count unit, a relative address of necessary information on the reception buffer and one of pseudo current addresses from the current address generation unit are selected according to the select signal, The message transmitting / receiving apparatus according to claim 1, further comprising a current address selector for sending to the buffer address generating unit.