JP2000003332A - Bi-directional bus size conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bi-directional bus size conversion circuit which minimizes the conversion time. SOLUTION: The bi-directional bus size conversion circuit 1 which incorporates a bus sizing function is composed of a bus size conversion circuit 2 having a bus sizing (a bus size conversion) function from a bus line A to a bus line B and a bus size conversion circuit 3 having the bus sizing function from the bus line B to the bus line A. The bus size conversion circuits 2 and 3 are composed of a FIFO memory as a main body, converts input data of, for example, 8 bit, into data of 4×8=32 bit in a form for successive/parallel converting and, on the contrary, converts the input data of, for example, 32 bit, into the data of 8 bit in the form of parallel/successive converting.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bidirectional bus size conversion circuit, and more particularly to a bidirectional bus size conversion circuit in a computer system.

[0002]

2. Description of the Related Art As shown in FIG. 6, for example, a printer device of a computer system has a central processing unit (CPU; computer) 25 for controlling the entire system, and a RAM (random access memory) for storing data and control programs. 26, ROM (read only memory) 2
7. A peripheral control circuit (CTRL) 28, for example, a hard disk drive (HD) 29 for storing fonts and the like, a common bus 30, HD 29 for interconnecting these circuits (devices)
And a common bus 30.

Now, for example, if the bus size of the common bus 30 is 32 bits (width) and the interface bus size of the HD 29 is 8 bits (width), the bidirectional bus size conversion circuit 1 converts the 32-bit data into 32-bit data. It is necessary to have an 8-bit / 8-bit → 32-bit bus size conversion function.

Conventionally, when the input bus size is different from the output bus size, bus sizing is performed programmatically (software) by firmware, or a bus sizable CPU is employed to convert the bus size.

[0005] For example, Japanese Patent Application Laid-Open No. Hei 2-253362 discloses a CPU having a 32-bit bus capable of bus sizing.
, A bus sizing operation by an address mapping method using an 8-bit FIFO (first-in first-out memory) has been proposed.

[0006]

In the prior art, for example, in the proposal described in Japanese Patent Application Laid-Open No. Hei 2-253362, since byte access is performed and bus sizing is processed by a program, there is a problem that data transfer takes time. is there. In other words, when the CPU bus width is 2 ⁿ bits (n = 4, 5, 6,...), For example, when converting to an 8-bit bus of a hard disk, 2 ⁿ ÷ 8 CPU accesses are required, When handling a large amount of data such as, for example, it takes an extremely long time.

Also, a CPU having a bus sizing function
In the case of bus sizing by
There is a problem in that the freedom of CPU selection is lost. That is,
In the case of address mapping, a bus sizing function added to the CPU is an essential condition.

An object of the present invention is to provide a bidirectional bus size conversion circuit that minimizes conversion time.

[0009]

SUMMARY OF THE INVENTION A bidirectional bus size converter according to the present invention is a bidirectional bus size converter for interconnecting bus lines having different bus sizes. When converting the bus size to a larger bus line, the first plurality of first-in first-out memories and the data from the smaller bus line are sequentially stored in the first plurality of first-in first-out memories. And first data output means for reading in parallel from the first plurality of first-in first-out memories and outputting the data as data of the bus line having the large bus size. And

When converting the bus size from the large bus line to the small bus line, a second plurality of first-in first-out memories and a second plurality of first-in first-out memories are provided. Second data writing means for writing data from the bus line with the larger bus size in parallel to a first-out memory; and data on the bus line with the smaller bus size sequentially read from the second plurality of first-in first-out memories. And a second data output means for outputting the data as a second data output means.

Further, a signal for permitting data reading is output when at least one set of data is written in the first and second plurality of first-in first-out memories.

Still further, when the first and second plurality of first-in first-out memories are filled with data, writing to the first and second plurality of first-in first-out memories is prohibited. It is characterized by outputting an alarm.

The operation of the present invention is as follows. Bus sizing is performed by writing data having different data bit widths to the FIFO and reading the data from the opposite data bus. Therefore, it is not necessary to perform bus sizing by software, and it is not necessary to select a CPU having a bus sizing function.

For example, bus sizing from 32-bit width data to 8-bit width data, for example,
Bus sizing is performed by writing 32-bit data once to the 32-bit width data bus and reading data four times from the 8-bit width data bus of FIF0.

For example, bus sizing from 8-bit width data to 32-bit width, for example, writes data four times to the 8-bit width data bus of FIFO0,
Bus sizing is performed by reading 32-bit data once from the 32-bit width data bus of F0.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a basic block diagram showing a configuration of an embodiment of a bidirectional bus size conversion circuit according to the present invention. In FIG. 1, a bidirectional bus size conversion circuit 1 having a bus sizing function according to the present invention includes a bus size conversion circuit 2 having a bus sizing (bus size conversion) function from a bus line A to a bus line B, and a bus line B.
From the bus line A to the bus line A.

FIG. 2 is a detailed block diagram of the bus size conversion circuit 2. In FIG. 2, the bus size conversion circuit 2
For example, an 8-bit width A input from the bus line A
FIFOs 8 to 11 for storing data, A for counting the number of times of writing A data written from bus line A
The write counter 5 includes an A write selector 4 that distributes a write signal (W) to FIFOs 8 to 11 based on a signal (S) from the A write counter 5.

A B read counter 6, an A write counter 5, and a B read counter 6 for counting the number of times of reading (for example, 4 × 8 bits) B1 to B4 data to the bus line B.
A comparator 7 compares the count value with the read counter 6 and generates a write enable signal to the bus line A (A write ready) and a read enable signal to the bus line B (B read ready).

Further, in synchronization with the B read signal, data B1 to B4 of 32 (4 × 8) bits are written on the bus line B.
It comprises output buffers 12 to 15 of FIFOs 8 to 11 for outputting to the outside.

FIG. 3 is a detailed block diagram of the bus size conversion circuit 3. In FIG. 3, bus size conversion circuit 3 includes 32 (4 × 8) bit data B 1 to B from bus line B.
FIFO that stores 4 in units of 8 bits
16 to 19, and an A read counter 20 for counting the number of readings of the FIFOs 16 to 19 to the bus line A.

The signals from the B write counter 21 and the A read counter 20, which count the number of times of writing to the FIFOs 16 to 19 from the bus line B,
The A read selector 22, which controls the output order of each 8-bit data of O16 to O19, compares the count values of the B write counter 21 and the A read counter 20, and outputs
And a comparator 23 that generates a write enable signal (B write ready) and a read enable signal (A read ready) to the bus line A.

Further, in synchronization with the A read signal, the bus line A is provided with a data output buffer 24 for outputting the output data of the FIFOs 16 to 19 in units of 8 bits according to the signal of the A read selector.

FIG. 6 is a system block diagram of a computer system related to the present invention, for example, a printer controller. As shown in FIG. 6, the computer system is a central processing unit and is a center of the printer controller. The CPU 25 manages and controls operations of a memory, an I / O interface, and the like, and executes all operations applied to data. The volatile memory temporarily stores print data and information for operating the CPU 25. It has a RAM 26.

The ROM 2 is a non-volatile memory storing instruction codes of the CPU 25, font data, and the like.
7. A controller circuit (CTRL) 28 that controls transmission and reception of data from outside the system as a printer controller and control signals for the CPU 25 to access the RAM 26 and the ROM 27.

Further, font information and other data of the printer are recorded, and a bidirectional bus size conversion circuit 1 is provided.
And a magnetic storage medium (hard disk; HD) 29 connected to the common bus 30 via the common bus 30.

In this case, the connection between the bidirectional bus size conversion circuit 1 and the common bus 30 is, for example, 32 bits, and the connection between the bidirectional bus size conversion circuit 1 and the HD 29 is, for example, 8 bits.
Is a bit.

The operation of the embodiment of the present invention will be described with reference to FIGS. In FIG. 2, when data on the bus line A side is transferred to the bus line B side (as shown in the timing diagram of FIG. 4), for example, 8-bit data A on the bus line A side
1, A2, A3, A4 are sequentially input to the A data bus,
With the data input, the A write signal becomes active "low;L" within the data valid time.

The A write signal is counted by the A write counter 5 as the number of times of writing, and the signal (S) of the counted number is passed to the A write selector 4. The A write selector 4 distributes and outputs the write signal (W) to the FIFOs 8 to 11 in order according to the count number. Thus, A
1 data is written to FIFO8, A2 data is
The A3 data is written to the FIFO 10 and the A4 data is written to the FIFO 11.

A5 to An data (n = 6, 7, 8,...) Input thereafter are similarly written to FIFOs 8 to 11 in order. The count value of the A write counter 5 is also passed to the comparator 7. At the same time as writing A4 data,
The 8-bit data is written four times, and the 32-bit data is generated to generate a B read ready (read permission) signal active “high; H” that enables the comparator 7 to read.

After confirming that the B read ready signal has become valid (active), a B read signal for outputting (data B1 to B4) to the bus line B is input. When the B read signal is input, the output buffers 12 to 15 of the FIFOs 8 to 11 are simultaneously in an output enable state, and the bus sized 32-bit data is used as the output data of the bidirectional bus size conversion circuit 1 to output the B read signal. It can be obtained during the period of active "low;L".

The B read counter 6 counts the B read signal as the number of times of reading, and the comparator 7 compares the number of times of writing with the number of times of reading.
As soon as there is no more data stored in, the B read ready signal is set to inactive “L” (reading prohibited).

Further, each of the FIFOs 8 to 11 has the same FIFO depth (storage capacity). The FIFOs 8 to 11 are written the same number of times. By setting the write ready to inactive “L” (write inhibit),
It is possible to warn the system of the loss of the data in the FIFOs 8 to 11 due to the write overflow. Thus, the 8-bit data on the bus line A side is
Bus sizing and reading are performed as 32-bit data on the bus line B side.

In FIG. 3, data B on the bus line B side
When the data B1 to B4 are transferred to the bus line A side (as shown in FIG. 5), the B data B1 to B4 are arranged in parallel (in FIG.
(Only shown as a representative) is input to the B data bus, and together with the data input, the B write signal becomes active "L" within the data valid time. As a result, 32-bit B data B1 to B4 are simultaneously written into FIFOs 16 to 19 in 8-bit units. The B write signal is counted by the B write counter 21, and the result counted by the B write counter 21 is passed to the comparator 23 as the number of times of writing.

The comparator 23 activates an A read ready (read permission) signal indicating that there is data written in the FIFOs 16 to 19 but not read out, that is, that the bus line A side is readable. H ”. Next, the data read on the bus line A side is performed by the read enable signal, and the A data A1 to A data A
4 are sequentially read.

At this time, the A read signal is counted by the A read counter 20, and the A read selector 22 receiving the count signal puts the A read signal on the output data bus on the bus line A side.
The data of FIFO16 is selected at the timing of one data read, and the data of FIFO1 is selected at the timing of A2 data read.
7 data, FIFO at A3 data read timing
18 data, FIF at A4 data read timing
Each of the data stored in O19 is selected.

In synchronization with the selection timing of each data, the data output buffer 24 on the bus line A drives the selected data to the data bus on the bus line A, and the 32-bit data is transferred to the 8-bit bus. A sized result can be obtained.

Each of the FIFOs 16 to 19 has the same FIFO depth. The FIFOs are written the same number of times, and if no reading is performed during that time, the comparator 23 outputs a write enable signal write ready signal. By making inactive “L” (write protected), the FIFO
The system can be warned of loss due to 16-19 data write overflow. In this way, the 32-bit data on the bus line B side is bus-sized and read as 8-bit data on the bus line A side.

The bidirectional bus size conversion circuit 1 according to the present invention is connected between the common bus 30 and the HD 29 in FIG. For example, the connection between the bidirectional bus size conversion circuit 1 and the common bus 30 is a 32-bit bus width, and the connection to the HD 29 is 8 bits.
The bit bus width.

When the CPU 25 attempts to store the data expanded in the RAM 26 memory in the HD 29,
The CPU 25 reads the data in the RAM 26 memory and sequentially writes 32-bit bus width data to the bidirectional bus size conversion circuit.

In the bidirectional bus size conversion circuit 1, the read ready signal to the 8-bit bus becomes active "H" by writing to the 32-bit side. The CTRL 28 generates a read signal of the 8-bit bus and a write signal to the HD 29 of the bidirectional bus size converter 1 in response to the read ready signal of the 8-bit bus becoming active. The data stored inside is
It is written to the HD 29 as 8-bit data in the order of accumulation.

This operation is continued until the read ready signal to the 8-bit bus becomes inactive "L". In this case, the CPU 25 writes the data of the RAM 26 to the bidirectional bus size conversion circuit 1 in order on the 32-bit side bus of the bidirectional bus size conversion circuit 1 so that the HD is not bus-sized by software, and
29 can be written.

Next, when the CPU 25 attempts to read data in the HD 29, the CPU 25 outputs a read signal to the 32-bit bus of the bidirectional bus size conversion circuit 1. Therefore, the CTRL 28 generates a read signal from the HD 29 and a write signal to the 8-bit bus of the bidirectional bus size conversion circuit 1 four times, and the 8-bit data is arranged as 32-bit data inside the bidirectional bus size conversion circuit 1. At that point, it is taken into the 32-bit bus of the CPU 25. The 8-bit data from the HD 29 is bus-sized to 32-bit data when it is taken into the CPU 25, and can be written to the RAM 26 without bus sizing by software.

By adding an address generator for performing DMA, a circuit for receiving a DMA request and generating an acknowledge, and a circuit for generating a read signal and a write signal in synchronization with the acknowledge to the CTRL 28 circuit of FIG. By using the bidirectional bus size conversion circuit 1 according to the present invention, an efficient data transfer circuit can be configured.

When transferring the 32-bit data of the RAM 26 to the 8-bit bus HD 29, the CTRL 28 circuit monitors “H” at which the 32-bit bus write ready signal of the bidirectional bus size conversion circuit 1 is writable.
If writable, a read signal for sequentially reading data from the RAM 26 and its address signal are output, and at the same time, a write signal to the 32-bit side bus of the bidirectional bus size conversion circuit 1 is output.

Thus, the data in the RAM 26 is stored in the bidirectional bus size conversion circuit 1. The data written in the bidirectional bus size conversion circuit 1 is a read-ready readable logic “H” signal of the 8-bit side bus DM.
A request, the CTRL 28 DMA circuit sends the 8-bit side bus read signal of the bidirectional bus size conversion circuit 1 and the HD
A write signal to the HD 29 is generated and written to the HD 29 in the order of accumulation in the bidirectional bus size conversion circuit 1. Therefore, the data in the RAM 25 is bus-sized by the bidirectional bus size conversion circuit 1 without control by the CPU 25, and
It can be stored in the HD 29.

Next, when transferring the 8-bit data of the HD 29 to the RAM 26 via the 32-bit bus, the CTRL
The 28 circuit monitors “H” at which the 8-bit bus write ready signal of the bidirectional bus size conversion circuit 1 is writable.
29, and a write signal to the 8-bit bus of the bidirectional bus size conversion circuit 1 is output.

Thus, the data of the HD 29 is stored in the bidirectional bus size conversion circuit 1. The data written in the bidirectional bus size conversion circuit 1 is a read-ready readable “H” signal of the 32-bit side bus DM.
A request, the CTRL 28 DMA circuit sends the 32-bit bus read signal of the bidirectional bus size conversion circuit 1 and R
A write signal to the AM 26 and a write address to the RAM 26 are generated and written to the RAM 26 in the order of accumulation in the bidirectional bus size converter 1.

Therefore, without control by the CPU 25, the HD
The 29 data can be bus-sized by the bidirectional bus size conversion circuit 1 and stored in the RAM 26. In this case, C
Since there is no reading of the bidirectional bus size conversion circuit 1 from the PU 25, when reading from the CPU 25, there is no time to wait until data on the HD 29 side is read four times, and the use time of the common bus 30 is reduced by a quarter. Can be reduced to time.

[0049]

As described above, the present invention has an effect that bus-sized data can be obtained immediately in data transfer between devices having different data bit widths. That is, a circuit having a function of performing bus sizing is built in the bidirectional bus size conversion circuit.

[Brief description of the drawings]

FIG. 1 is a basic block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of an 8-bit / 32-bit bus size conversion circuit.

FIG. 3 is a block diagram of a 32-bit / 8-bit bus size conversion circuit.

FIG. 4 is a timing chart of an 8-bit / 32-bit bus size conversion circuit.

FIG. 5 is a timing chart of a 32-bit / 8-bit bus size conversion circuit.

FIG. 6 is a block diagram of a related computer system of the present invention.

[Description of Signs] 1 Bidirectional bus size conversion circuit 2, 3 Bus size conversion circuit

Claims (4)

[Claims] 1. A bidirectional bus size conversion circuit for mutually connecting bus lines having different bus sizes, wherein the bus size is converted from a bus line having a small bus size to a bus line having a large bus size. A first plurality of first-in first-out memories; first data writing means for sequentially writing data from the bus line having the smaller bus size to the first plurality of first-in first-out memories; A first data output means for reading in parallel from the first-in first-out memory and outputting the data as data of the bus line having the large bus size. 2. The method according to claim 2, wherein the bus size is converted from a bus line having a large bus size to a bus line having a small bus size. Second data writing means for writing data from the bus line with the larger bus size in parallel to a first-out memory; and data on the bus line with the smaller bus size sequentially read from the second plurality of first-in first-out memories. 2. A bidirectional bus size conversion circuit according to claim 1, further comprising: a second data output means for outputting the data as a data. 3. The method according to claim 1, wherein when at least one set of data is written in the first and second plurality of first-in first-out memories, a signal for permitting data reading is output. 2. The bidirectional bus size conversion circuit according to 2. 4. When the first and second pluralities of first-in first-out memories are filled with data, writing to the first and second pluralities of first-in first-out memories is inhibited and an alarm is issued. 4. The bidirectional bus size conversion circuit according to claim 1, wherein