JPH09185882A - First-in first-out memory device with different size of input output data and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an output of data with a different size from that of input data by using a pointer so as to conduct write/read to/from an FIFO when the size of the input data for write and the size of data to be read differ from each other. SOLUTION: An input section 100 receives data DI corresponding to a mode control signal MOD and provides an output of a data string DBI. A generating section 400 generates a write pointer and a read pointer corresponding to the signal MOD and a buffer 200 is made up of a register block. When the size of data read and outputted is larger than the size of written input data, a write pointer with an incremental width set in advance and a read pointer with a larger incremental width than that of the write pointer are generated. In this case, the incremental width of the read pointer is larger than the incremental width of the write pointer by a ratio of the size of the input data to the size of the output data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a first-in first-out memory device, and more particularly to a first-in first-out memory device in which the size of input data and the size of output data are different and a method thereof.

[0002]

2. Description of the Related Art It is necessary to buffer and temporarily hold data transmitted in a data processing system or data from an external system. This need arises because the receiver is performing another operation when the data is received, or the data transfer rates of the transmitter and the receiver are different from each other. What has emerged to solve this need is first-in first-in memory
t-Out Memory: Hereinafter referred to as "FIFO". ). The FIFO outputs the first input data first and outputs the last input data last. The operation is performed by RS latch or read / write. It is generally controlled by a pointer.

FIG. 1 shows the data input / output operation of the FIFO by R
It is a figure which shows the structure of the FIFO device according to the prior art which controls using an S latch. In the figure, the FIFO device controls a series of registers for storing the input data D0 to D3 and the series of registers to store the input data D0 to D3, and stores the stored data Q0 to Q0.
And a circuit for controlling the operation output as Q3. The control circuit includes a series of RSs corresponding to the respective registers.
It consists of a latch and control logic that controls the operation of a series of RS latches.

FIG. 2 is a diagram showing the structure of a FIFO device according to the prior art which controls the data input / output operation of the FIFO using a read pointer and a write pointer. In the figure, the input data D (n) is stored in the dual port RAM array through the data input buffer, and the data stored in the dual port RAM is output as data Q (n) through the data output buffer. At this time, the area of the dual port RAM array storing the data is designated by the write pointer, and the data stored in the area of the dual port RAM array designated by the read pointer is output. The flag logic then determines how much data is stored in the dual-port RAM array, or in other words, when the dual-port RAM array is not storing any data, the empty logic.
If a flag is generated and data is stored in all areas of the dual port RAM array, a full flag is generated. Write control and read control are
The write enable signal WEN and the read enable signal REN are input, respectively, and the flag indicating the storage state of the dual port RAM array is input from the flag logic to control the operation of the write pointer and the read pointer.

As described above, in the FIFO device according to the conventional technique applied to the ordinary data processing system,
The operation of inputting data to O to write it and outputting the written data is controlled by the RS latch or the write / read pointer. In this case, the size of the input data and the size of the output data are the same. However, when the input data size and the output data size are different, there is a problem that such a FIFO device cannot be applied. For example, in a CD-ROM decoder, data transmission is performed with 8 bits when performing internal data processing and interface between an external RAM and a microcomputer, but when performing interface with a host computer, data transmission is performed with 8 bits or 16 bits. Therefore, when the FIFO device according to the prior art is applied to such a CD-ROM, there is a problem that smooth data processing is difficult.

[0006]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a FIFO device which outputs data having a size different from that of input data. Another object of the present invention is to provide a FIFO device applicable when the size of input data is larger than the size of output data.

Another object of the present invention is to provide a FIFO device applicable when the size of output data is larger than the size of input data. Still another object of the present invention is to use a generated pointer after generating a write pointer and a read pointer corresponding to the difference between the input data size and the output data size in the FIFO device. It is to provide a method of processing input / output data.

[0008]

In order to achieve such an object, in a FIFO device according to the present invention, the size of input data for writing differs from the size of data read and output. In this case, after generating a write pointer having a preset increment and a read pointer that is larger or smaller than the increment of the write pointer, input data is written to the FIFO using the generated write pointer. Writing is performed, and the input data written in the FIFO is read using the generated read pointer and output as output data.

According to the first operation of the present invention, when the size of the data read and output is larger than the size of the input data for writing, the FIFO device writes with a preset increment width. A pointer and a read pointer larger than the increment of the write pointer are generated. At this time, the increase width of the read pointer is larger than the increase width of the write pointer by a ratio corresponding to the ratio of the size of the input data to the size of the output data.

According to the second operation of the present invention, when the size of the input data for writing is larger than the size of the data to be read and output, the FIFO device writes with a preset increment. A pointer and a read pointer smaller than the increment of the write pointer are generated. At this time, the increase width of the write pointer is larger than the increase width of the read pointer by a ratio corresponding to the ratio of the size of the input data to the size of the output data.

In the FIFO device according to the present invention, the input data DI corresponding to the external mode control signal MOD, which is determined according to the sizes of the input data and the output data, has a predetermined size. A data input section for outputting as a data string DBI, a pointer generating section for generating a write pointer Wptr and a read pointer Rptr corresponding to the mode control signal MOD, and a large number of register blocks having a preset storage area. And a plurality of data strings DBI output from the data input unit are stored in the generated write pointer Wp.
A buffer that simultaneously writes or alternately writes to the storage area of each register block pointed by tr, and the data written in each register block of the buffer corresponding to the read pointer Rptr are read simultaneously or alternately. And an empty flag indicating the amount of data written in the buffer by using the write pointer Wptr and the read pointer Rptr, which are output as output data in a form corresponding to the mode control signal MOD. Or a flag generating section for generating a full flag.

[0012]

Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In the drawings, the same reference numerals and numbers are commonly used for the same components and parts. Further, in the description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention unnecessarily unclear. .

The terms used herein are defined as follows. “D1” indicates input data having a width (width) of 8 bits or 16 bits, and “D0” is
The output data having a size of 8 bits or 16 bits is shown. "DB1" indicates the input data of the buffer and "D1"
"B0" indicates the output data of the buffer. "MOD" can be changed according to the size of the input data and the output data as a mode control signal provided from the outside, for example, from the central processing unit (CPU). "" Indicates a write pointer, and input data is written in the storage area of the buffer pointed to by this pointer. "Rptr" indicates a read pointer, and the data written in the storage area of the buffer pointed by this pointer is output. "WE
“N” indicates a write enable signal provided for a write operation from the outside, and “REN” indicates a read enable signal provided for a read operation.
The "flag" indicates that data is written in all areas of the buffer, and the "empty flag" indicates that no data is written in any area of the buffer. Data size is 8
It is assumed that the number of bits is 16 bits. In other words, if both the input data and the output data are 8 bits, the input data is 8 bits and the output data is 6 bits.
An example will be described in which the input data is 16 bits, the output data is 8 bits, the input data and the output data are both 16 bits.

Referring to FIG. 3, a FIFO according to the present invention.
In the device, the data input unit 100 and the buffer 20
0, a data output unit 300, and a pointer and flag generation unit 400. The data input unit 100 has the configuration shown in FIG. 4, the buffer 200 has the configuration shown in FIG. 5, the data output unit 300 has the configuration shown in FIG. 6, and the pointer and flag generation unit 400 has the configuration shown in FIG.

In FIG. 4, the data input section 100 has eight
Input data DI with size of 16 bits or 16 bits
Are multiplexed by an input mode control signal IMOD which is a kind of selection signal, and buffer input data DBIH as a data string each having a size of 8 bits.
And output as DBIL. The input mode control signal I
The MOD is a signal whose level is determined in advance according to the size of the input data, and the data input unit 100 performs its operation based on this signal. Input data size is 8
If it is a bit, the data input unit 100 converts the input data DI [0: 7] into the buffer input data DBIL [0:
7] and DBIH [8:15]. On the other hand, when the size of the input data is 16 bits, the data input unit 100 outputs the input data DI [0: 7].
And DI [8:15] are buffer input data D
Output as BIL [0: 7] and DBIH [8:15].

In FIG. 5, the buffer 200 comprises a preset storage area, in other words, a register block 1 (210) and a register block 2 (220) each having a size of 4 bits. The buffer 200 is a buffer input data DB output from the data input unit 100.
Register block 2 pointed to by write pointer Wptr
Store in area 10, 220. When the input data DI is 8 bits, the buffer 200 alternates the buffer input data DBIH [0: 7] and DBIL [0: 7] to the register block 1 (210) and the register block 2 (220) according to the write pointer Wptr. Write. For example, the buffer input data DBI is 8 bits and 8 bytes are input, and these data are DBI0, DBI1, ...
, DBIH is DBI8, assuming DBI8
0, DBI2, ..., DBI8 data string, and D
BIL is a data string of DBI1, DBI3, ..., DBI7.

Therefore, the register block 1 (210) has an 8-bit 4-byte DBIH (DBI0, DBI0, DBIH).
2, DBI4, DBI6) are written to the register block 2 (220) and the 8-bit DBIL is 4 bytes.
(DBI1, DBI3, DBI5, DBI7) is written. On the other hand, if the input data DI is 16 bits, the buffer 200 is
IH [8:15] and DBIL [0: 7] are simultaneously written to the register block 1 (210) and the register block 2 (220) according to the write pointer Wptr. For example, assuming that the buffer input data DBI is 16 bits and 8 bytes are input, register block 1 (2
10) is a 16-bit 4-byte DBIH (DBIH
0, DBI1, DBI2, DBI3) are written to the register block 2 (220), and DBIL (DBI0, DBI1, DBI2, DBI) of 4 bytes of 16 bits is written.
3) is written. In FIG. 6, the data output unit 3
00 reads the data written in the area of the register block pointed by the read pointer Rptr as the data DB0, and then outputs it as the output data DOH and DOL having a form suitable for the size indicated by the output mode control signal OMOD. The output mode control signal OMOD is a signal whose level is determined in advance according to whether the size of the output data is 8 bits or 16 bits. When the output mode control signal OMOD indicates 8 bits, the data output unit 300 outputs the output data DOL.
When outputting only [0: 7] and indicating 16 bits, the data output unit 300 outputs the output data DOL [0: 7] and D.
OH [8:15] is output.

Referring to FIG. 7, the pointer and flag generator 400 comprises a write pointer generator 410, a read pointer generator 420, and a flag generator 430. The write pointer generator 410 receives a write enable signal WEN and an input mode control signal IM applied from the outside.
A write pointer Wp that points to a storage area of the buffer 200 for writing the buffer input data DBI using OD
generate tr. The read pointer generation unit 420 uses the read enable signal REN and the output mode control signal OMOD applied from the outside to set a read pointer Rptr that points to an area in the data written in the buffer 200, in which the data to be read is stored. To generate. The flag generation unit 430 uses the write pointer Wptr and the read pointer Rptr to generate a full flag and an empty flag indicating how much data is written in the buffer 200.

The operation of the FIFO device according to the present invention constructed as shown in FIGS. 3 to 7 for outputting output data having a size different from the size of input data will be described. First, the size of input data is 8 bits, and the size of output data is 1
If it is 6 bits, that is, if the size of the output data is larger than the size of the input data, the FIFO according to the present invention.
Operations performed by the apparatus will be described with reference to FIG.

As the output data to be read is larger than the input data to be written, the read pointer Rptr is increased more than the write pointer Wptr is increased. Increasing width of write pointer Wptr and read pointer Rptr
The difference between the increase width and the increase width corresponds to the ratio between the size of the input data and the size of the output data. If no data is written to the buffer 200 in the initial stage, the write pointer Wptr and the read pointer Rptr point to the address “000” of the buffer 200, as shown in FIG. When the write enable signal WEN is applied in such a state, the write pointer generation unit 410 generates the write pointer Wptr. In FIG. 8B, the write pointer Wptr
Indicates the address “011”. At this time, when the read enable signal REN is applied, the read pointer generator 420 also generates the read pointer Rptr. As a result, the data is written in the buffer 200 and the written data is read out. When data is written and read in the state as shown in FIG. 8B, the write pointer Wpt after a certain time (the pointer is increased by 3 steps).
r indicates the address “110”, and the read pointer Rpt
r indicates the address “100”. At this time, the values of the write pointer Wptr and the read pointer Rptr do not always indicate the address “110” and the address “100”, but may indicate the address “101” and the address “100”.

As shown in FIG. 8C, after the data write and read operations are simultaneously performed, as shown in FIG. 8D, the write pointer Wptr is preceded by the write pointer Wptr as compared with the read pointer Rptr. With 010 "pointing,
When the read pointer Rptr points to the address “010” (FIG. 8A), the flag generation unit 430 generates an empty flag. When the write pointer Wptr points to the address “011” and the read pointer Rptr points to the address “010”, the flag generation unit 430 (FIG. 8).
(B)) also generates an empty flag. This is because, in the latter case, the written data is 1 byte, but the read data is 2 bytes. That is, the total number of bytes written in 8 bits must be an even number. As shown in FIG. 8C, data write and read operations are simultaneously performed, and as shown in FIG. 8E, the read pointer Rp is larger than the write pointer Wptr.
When the write pointer Wptr also points to the address "100" while tr points to the address "110" first, the flag generator 430 generates a full flag. Because
This is because the data is written in all the areas of the buffer 200. In short, by making the increase width of the read pointer Rptr larger than the increase width of the write pointer Wptr, it is possible to output data having a size larger than the size of the input data.

Next, the size of the input data is 16 bits,
When the size of the output data is 8 bits, that is, when the size of the input data is larger than the size of the output data, the operation performed by the FIFO device according to the present invention will be described with reference to FIG. Since the size of the data is larger than the size of the output data to be read, the increase width of the write pointer Wptr is made larger than that of the read pointer Rptr. Write pointer Wp
The difference between the increment of tr and the increment of the read pointer Rptr corresponds to the ratio between the size of the input data and the size of the output data. If no data is written to the buffer 200 at the initial stage, the write pointer Wptr and the read pointer Rptr are set to the buffer 200 as shown in FIG.
Address "000". When the write enable signal WEN is applied in such a state, the write pointer generation unit 410 generates the write pointer Wptr.
In FIG. 9B, the write pointer Wptr points to the address “100”. At this time, when the read enable signal REN is applied, the read pointer generator 420 also generates the read pointer Rptr. Accordingly, data is written in the buffer 200 and the written data is read. When data is written and read in the state as shown in FIG. 9B, the write pointer Wpt is set after a certain time (the pointer is increased by one step).
r indicates the address “110”, and the read pointer Rpt
r indicates the address “010”.

As shown in FIG. 9C, the data write and read operations are simultaneously performed, and then the write pointer Wptr is moved to the address "01" as shown in FIG. 9D.
After that, when the read pointer Rptr points to the address “010”, the flag generator 430 generates an empty flag because the data written in all areas of the buffer 20 is read. After the data write and read operations are simultaneously performed as shown in FIG. 9C, the read pointer Rptr is first moved to the address "10" as shown in FIG.
0 ”. After that, when the write pointer Wptr points to the address“ 100 ”, the flag generation unit 430 becomes full.
Generate a flag. The flag generation unit 430 increases the pointer value by three steps and the address "101" as a matter of course when the read pointer Rptr points to the address "010".
Will also generate a full flag. because,
This is because even if the area of the buffer 200 indicated by the write pointer Wptr is smaller than the area indicated by the read pointer Rptr by 1 byte, 1 byte of data is lost unless it is determined that the buffer 200 is full.

In short, by making the increase width of the write pointer Wptr larger than the increase width of the read pointer Rptr, data having a size smaller than the size of the input data can be output. The operation according to the present invention can be applied to the case where the input data size and the output data size are the same. In this case, the size of the input data and the size of the output data may all be 8 bits, and the size of the input data and the size of the output data may all be 16 bits.

Next, such an operation will be described with reference to FIG. 10 showing a case where the size of input data and the size of output data are all 8 bits. Since the size of the input data to be written and the size of the output data to be read are the same, the increment of the write pointer Wptr and the increment of the read pointer Rptr are the same. If no data is written to the buffer 200 at the initial stage, the process shown in FIG.
As shown in (A), the write pointer wptr and the read pointer Rptr are stored at the address “00” of the buffer 200.
0 ”. When the write enable signal WEN is applied in such a state, the write pointer generation unit 410
Generates a write pointer Wptr. FIG. 10 (B)
, The write pointer Wptr has the address "01".
1 ”. At this time, when the read enable signal REN is applied, the read pointer generation unit 420 also generates the read pointer Rptr.
The data is written in and the written data is read out. When data is written and read in the state shown in FIG. 10B, the write pointer Wptr points to the address “101” and the read pointer Rptr to the address “101” after a certain time (the pointer is increased by two steps). 011 ". As shown in FIG. 10C, the data writing and reading operations are performed at the same time, and then the data shown in FIG.
As shown in (D), the write pointer Wptr points to the address "001" first. After that, the read pointer Rp
When tr points to the address “001”, the flag generator 43
0 generates an empty flag. This is because the data written in all areas of the buffer 200 has been read. As shown in FIG.
After simultaneously performing data write and read operations,
As shown in FIG. 10E, the read pointer Rptr points to the address “101”. After that, the write pointer W
When ptr points to the address “101”, the flag generator 4
30 generates a full flag.

In short, by making the increase width of the write pointer Wptr and the increase width of the read pointer Rptr the same, it is possible to output data having the same size as the input data. On the other hand, the flag generator 430 is set to "1" when the write pointer Wptr points to the address "111" and then to the address "000", and the read pointer Rptr points to the address "111" and then to the address "000". If it indicates "", it has a flag that is cleared to "0", but the write pointer Wpt
When the address indicated by r and the address indicated by the read pointer Rptr are the same, if the flag state is "0", an empty flag is generated and the write pointer Wp is generated.
If the address pointed to by tr and the address pointed by read pointer Rptr are the same, and the flag state is "1", a full flag is generated.

Although the specific embodiments according to the present invention have been described above, various modifications and changes can be made without departing from the technical idea of the present invention. It will be obvious to anyone with ordinary knowledge in the field. That is, the present invention has specifically described only the case where the size of the input / output data is 8 bits or 16 bits. However, the present invention can be applied even when the size of input / output data is 8, 16 or 32 bits. In this case, 4 buffers
It is possible to configure by using the register blocks and to appropriately select the ratio between the increase width of the write pointer and the increase width of the read pointer according to the ratio of the input / output data.
Therefore, the scope of the present invention is not limited to the described embodiments, and should be determined not only by the scope of the claims but also by the equivalents of the claims.

[0028]

As described above, in the first-in first-out memory device according to the present invention, the increase width of the write pointer pointing to the area for writing the input data and the increase width of the read pointer pointing to the area for reading the written data are different. This has the advantage that data of a size different from the size of the input data can be output.

[Brief description of the drawings]

FIG. 1 shows the data input / output operation of the first-in first-out memory by RS.
FIG. 3 is a configuration diagram of a first-in first-out memory device according to a related art which is controlled by using a latch.

FIG. 2 is a block diagram of a first-in first-out memory device according to the prior art for controlling the data input / output operation of a first-in first-out memory using a read / write pointer.

FIG. 3 is a block diagram of a first-in first-out memory device according to the present invention.

FIG. 4 is a detailed configuration diagram of a data input unit shown in FIG.

5 is a detailed configuration diagram of the buffer shown in FIG.

FIG. 6 is a detailed configuration diagram of a data output unit shown in FIG.

FIG. 7 is a detailed configuration diagram of a pointer and flag generation unit shown in FIG.

FIG. 8 is a diagram for explaining the first operation of the present invention.

FIG. 9 is a diagram for explaining the second operation of the present invention.

FIG. 10 is a diagram for explaining the third operation of the present invention.

[Explanation of symbols]

 100 data input unit 200 buffer 300 data output unit 410 write pointer generation unit 420 read pointer generation unit 430 flag generation unit

Claims (15)

[Claims] 1. Data input means for outputting input data as a large number of data strings having a preset size in response to an external mode control signal determined according to the sizes of input data and output data. Pointer generating means for generating a write pointer and a read pointer corresponding to the mode control signal, and a large number of data strings output from the data input means, which are composed of a large number of register blocks having preset storage areas. Writing to the storage area of each of the register blocks pointed to by the generated write pointer at the same time,
Alternatively, the buffer means for writing alternately and the data written in each register block of the buffer means corresponding to the read pointer are read at the same time, or alternately read out, and then output in the form corresponding to the mode control signal. First-in first-out, characterized in that it comprises data output means for outputting as data, and flag generation means for generating a flag indicating the amount of data written in the buffer means using the write pointer and the read pointer. Memory device. 2. The data input means, when the mode control signal indicates that the size of the output data is larger than the size of the input data, sets the data string having the size of the input data as the size of the output data. 2. The apparatus according to claim 1, wherein the output is repeated until the same. 3. The pointer generation means generates a write pointer having an increase width corresponding to the mode control signal, and generates a read pointer having an increase width larger than the increase width of the generated write pointer. The apparatus of claim 2 characterized. 4. The increase width of the read pointer is larger than the increase width of the write pointer by a ratio corresponding to the ratio of the size of the input data to the size of the output data. apparatus. 5. The buffer means has a large number of register blocks having the same storage area as the size of the input data, and alternates the data string to each of the register blocks corresponding to the generated write pointer. The device according to claim 4, characterized in that 6. The data output means alternately reads the data written in each register block of the buffer means in correspondence with the read pointer, and then outputs the data as output data in a form corresponding to the mode control signal. The device according to claim 5, wherein the device outputs. 7. The data input means, when the mode control signal indicates that the size of the input data is larger than the size of the output data, outputs the input data to a plurality of data strings having the size of the output data. The device according to claim 1, wherein the device is divided and outputted. 8. The pointer generation means generates a write pointer having an increase width corresponding to the mode control signal, and generates a read pointer having an increase width smaller than the increase width of the generated write pointer. The device of claim 7 characterized. 9. The increase width of the read pointer is smaller than the increase width of the write pointer by an amount corresponding to a ratio of the size of the input data to the size of the output data. apparatus. 10. The buffer means has a large number of register blocks having the same storage area as the size of the output data, and the data string is simultaneously stored in each of the register blocks corresponding to the generated write pointer. The device according to claim 9, wherein writing is performed. 11. The data output means simultaneously reads the data written in each register block of the buffer means in correspondence with the read pointer, and then outputs it as output data in a form corresponding to the mode control signal. The device according to claim 10, characterized in that 12. In an input / output data processing method of a first-in first-out memory device for writing / reading data to / from a first-in first-out memory by using a write pointer and a read pointer, the input data for writing is read out and output. If the size of the data to be stored is large, a write pointer having a preset increment, a pointer generation process for generating a read pointer larger than the increment of the write pointer, and input using the generated write pointer A data writing step of writing data in the first-in first-out memory, and a data reading step of reading out the input data written in the first-in first-out memory using the generated read pointer and outputting it as output data. Input / output data processing method. 13. The increase width of the read pointer is larger than the increase width of the write pointer by a ratio corresponding to the ratio of the size of the input data to the size of the output data. Method. 14. In an input / output data processing method of a first-in first-out memory device for writing / reading data to / from a first-in first-out memory by using a write pointer and a read pointer, the size of input data for writing is read. A write pointer having a preset increment and a read pointer smaller than the increment of the write pointer when the output data is larger than the output data; and input data using the generated write pointer. In the first-in first-out memory, and a data reading step of reading out the input data written in the first-in first-out memory using the generated read pointer and outputting it as output data. Input / output data processing method. 15. The increase width of the write pointer is larger than the increase width of the read pointer by a ratio corresponding to the ratio of the size of the input data to the size of the output data. Method.