GB2307069A

GB2307069A - First-in first-out memory device enabling sizes of input/output data to be different from each other

Info

Publication number: GB2307069A
Application number: GB9622946A
Authority: GB
Inventors: Ki-Hong Kim
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1995-11-04
Filing date: 1996-11-04
Publication date: 1997-05-14
Anticipated expiration: 2016-11-04
Also published as: GB9622946D0; JPH09185882A; GB2307069B; KR970029070A; CN1154511A; CN1078720C

Abstract

A first-in first-out memory device which outputs data for enabling sizes of input data and output data to be different from each other. The first-in first-out memory device, includes: a data input unit (100) for outputting input data as a plurality of data strings having a preset size in correspondence with an external mode control signal determined by the size of the input data and the output data; a pointer generating unit (400) for generating a write pointer and a read pointer in correspondence with the mode control signal; a buffering unit (200) composed of a plurality of register blocks (210, 220) having a preset storage area, for concurrently or alternately writing the plurality of data strings output from the data input unit (100) on the storage area of each of the register blocks (210, 220) indicated by the generated write pointer; a data output unit (300) for concurrently or alternately reading the data written on each register block (210, 220) of the buffering unit (200) in correspondence with the read pointer, to thereby output as output data having a format corresponding to the mode control signal; and a flag generating unit (400) for generating a flag indicating the amount of the data written on the buffering unit (200) by using the write pointer and the read pointer.

Description

FIRST-IN FIRST-OUT MEMORY DEVICE FOR ENABLING SIZES OF INPUT/OUPUT DATA TO BE DIFFERENT FROM EACH OTHER AND METHOD THEREFOR The present invention relates to a first-in first-out memory (hereinafter, referred to as FIFO) device, and more particularly, though not exclusively, to a FIFO device for enabling sizes of input data and output data to be different from each other and a method therefor.

In a data processing system, it is required to buffer and temporarily hold data to be transmitted or data provided from an external system. This need results from the fact that a receiver performs other operation when the data is received or the data transmission ratios of a transmitter and the receiver are different from each other. A first-in first-out memory is suggested to meet such needs. The FIFO performs an operation of enabling first input data to be first output data and of enabling latest input data to be latest input data. Such an operation is generally controlled by an RS latch or a read/write pointer.

Figure 1 is a block diagram illustrating the structure of a prior art first-in first-out memory device which controls data input/output operations thereof by using an RS latch.

Referring to Figure 1, the FIFO device includes a row of registers for storing input data DO-D3 and a control circuit for storing the input data DO-D3 in said row of registers and for outputting the stored input data DO-D3 as output data QO-Q3. The control circuit comprises a row of RS latches corresponding to each register and control logic for controlling operations of the RS latches.

Figure 2 is a block diagram illustrating the structure of another prior art first-in first-out memory device which controls data input/output operations thereof by using read/write pointers.

Referring to Figure 2, input data D(n) is stored in a dual port RAM array through a data input buffer and the data stored in a dual port RAM is outputted through a data output buffer as data Q(n). At this time, the area of the dual port RAM array where the data is stored is indicated by a write pointer and the data stored in the area of the dual port RAM array, which is indicated by a read pointer, is outputted. A flag logic determines how much data is stored in the dual port RAM array, and then, generates an empty flag EF when there is no data stored in the dual port RAM array and a full flag FF when data is stored in all the area of the dual port RAM array.Write control and read control receive a write enable signal WEN and a read enable signal REN, respectively, and control the operations of the write pointer and the read pointer by inputting from the flag logic, a flag indicating the storage state of the dual port RAM array.

According to the FIFO device based on the prior art applied to the above-mentioned conventional data processing system, the operations of inputting and writing data and outputting the written data are controlled by the RS latch or the write/read pointers. In this case, the sizes of the input data and the output data are congruous with each other. However, when the sizes of the input data and the output data are different from each other, it results in a problem in that such a FIFO device can not be utilised. For example, in a compact disk ROM (CD-ROM) decoder, while data transmission is performed by 8 bits during the internal data processing and interfacing between the external RAM and a microcomputer, the data transmission upon interfacing with the host computer is performed by 8 bits or 16 bits.Thus, when the FIFO device according to the prior art is applied to such a CD-ROM, it is troublesome to process data smoothly.

It is an aim of preferred embodiments of the present invention to provide a FIFO device which outputs data for enabling sizes of input data and output date to be different from each other.

It is another aim of preferred embodiments of the present invention to provide a FIFO device which can be applied in the case that the size of input data is larger than that of the output data.

It is yet another aim of preferred embodiments of the present invention to provide a FIFO device which can be applied in the case that the size of output data is larger than that of the input data.

It is further yet another aim of preferred embodiments of the present invention to provide a method for, when the sizes of the input data and output data are different form each other, generating corresponding write and read pointers with using the generated pointers and processing input/output data in FIFO device.

According to the present invention in a first aspect, there is provided a first-in first-out memory device, comprising: a data input unit for outputting input data as a plurality of data strings having a preset size in correspondence with an external mode control signal determined by the size of the input data and the output data; a pointer generating unit for generating a write pointer and a read pointer in correspondence with said mode control signal; a buffering unit composed of a plurality of register blocks having a preset storage area, for concurrently or alternately writing the plurality of data strings output from said data input unit on the storage area of each of said register blocks indicated by said generated write pointer; a data output unit for concurrently or alternately reading the data written on each register block of said buffering unit in correspondence with said read pointer, to thereby output as output data having a format corresponding to said mode control signal; and a flag generating unit for generating a flag indicating the amount of the data written on said buffering unit by using said write pointer and said read pointer.

Suitably, said data input unit repeatedly outputs the data string having a size of said input data until the size becomes congruous with that of said output data when said mode control signal indicates that the size of said output data is larger than that of said input data size.

Suitably, said pointer generating unit generates a write pointer having an increment corresponding to said mode control signal and a read pointer having an increment larger than that of said generated write pointer.

Suitably, the increment of said read pointer is as large as the ratio of the size of said input data to the size of said output data, rather than the increment of said write pointer.

Suitably, said buffering unit has a plurality of register blocks having the storage area same as the size of the input data and said data string is alternately written on each register block corresponding to said generated write pointer.

Suitably, said data output unit alternately reads the data written on each register block of said buffering unit corresponding to said read pointer and then outputs the read data as output data having a format corresponding to said mode control signal.

Suitably, when said mode control signal indicates that the size of the input data is larger than that of the output data, said data input unit divides the input data into a plurality of data strings having the size of said output data, to thereby output the divided input data.

Suitably, said pointer generating unit generates a write pointer having an increment corresponding to said mode control signal and a read pointer having an increment less than that of the generated write pointer.

Suitably, the increment of said read pointer is as small as the ratio of the size of said input data and the size of said output data rather than the increment of said write pointer.

Suitably, said buffering unit has a plurality of register blocks having the storage area same as the size of the output data and said data string is concurrently written on each register block corresponding to said generated write pointer.

Suitably, said data output unit concurrently reads the data written on each register block of said buffering unit corresponding to said read pointer and then outputs the read data as output data having a format corresponding to said mode control signal.

According to the present invention in a second aspect, there is provided a method for processing input/output data of a first-in first-out memory device which performs data writing and reading operations by using a write pointer and a read pointer, said method comprising the steps of: generating a write pointer having a preset increment and a read pointer having an increment larger than that of said write pointer when the size of output data to be read is larger than that of input data to be written; writing said input data on said first-in first-out memory by using said generated write pointer; and reading said input data written on said first-in first-out memory by using said generated read pointer, to thereby output the read input data as output data.

Suitably, the increment of said read pointer is as large as the ratio of the size of said input data and the size of said output data rather than the increment of said write pointer.

According to the present invention in a third aspect, there is provided a method for processing input/output data of a first-in first-out memory device which performs data writing and reading operations by using a write pointer and a read pointer, said method comprising the steps of: generating a write pointer having a preset increment and a read pointer having an increment less than that of said write pointer when the size of input data to be written is larger than that of output data to be read; writing said input data on said first-in first-out memory by using said generated write pointer; and reading said input data written on said first-in first-out memory by using said generated read pointer, to thereby output the read input data as output data.

Suitably, the increment of said write pointer is as large as the ratio of the size of said input data and the size of said output data rather than the increment of said read pointer.

According to the present invention in a fifth aspect, there is provided a first-in first-out memory device, comprising a storage area and means for adaptively inputting and outputting data according to the size of the input and output data respectively.

Suitably, the first-in first-out memory device further comprises any one or more of the features of the accompany description, claims, abstract and/or drawings in any combination.

According to a fourth aspect of the present invention, there is a provided a first-in first-out memory device which generates a write pointer having a preset increment and a read pointer having an increment larger or smaller than the write pointer when the size of output data to be read is different from that of input data to be written, writes the input data on the first-in first-out memory by using the generated write pointer, and reads the input data written on the first-in first-out memory by using the generated read pointer, to thereby output the read input data as output data.

According to a first operation of the present invention, the first-in first-out memory generates a write pointer having a preset increment and a read pointer having an increment larger than that of the write pointer when the size of output data to be read is larger than that of input data to be written. At this stage, the increment of the read pointer is as large as the ratio of the size of the input data and the size of the output data rather than the increment of the write pointer.

According to a second operation of the present invention, the first-in first-out memory generates a read pointer having a preset increment and a write pointer having an increment larger than that of the read pointer when the size of output data to be read is smaller than that of input data to be written. At this stage, the increment of the write pointer is as large as the ratio of the size of the input data and the size of the output data rather than the increment of the read pointer.

A more complete appreciation of this invention, and many of the attendant advantages thereof, will be readily apparent as the same becomes better understood by reference to the following detailed description, provided by way of example only, when considered in conjunction with the accompanying drawings, in which like reference symbols indicate the same or similar components, wherein:: Figure 1 is a block diagram illustrating the structure of a prior art first-in first-out memory device which controls data input/output operations thereof by using an RS latch; Figure 2 is a block diagram illustrating the structure of another prior art first-in first-out memory device which controls data input/output operations thereof by using read/write pointers; Figure 3 is a block diagram illustrating the structure of a first-in first-out memory device according to the present invention; Figure 4 is a detailed diagram illustrating the structure of the data input unit of Figure 3; Figure 5 is a detailed diagram illustrating the structure of the buffer of Figure 3; Figure 6 is a detailed diagram illustrating the structure of the data output unit of Figure 3; Figure 7 is a detailed diagram illustrating the structure of the pointer and flag generator of Figure 3;; Figure 8 is a view for explaining a first operation of the present invention; Figure 9 is a view for explaining a second operation of the present invention; and Figure 10 is a view for explaining a third operation of the present invention.

Throughout the drawings, it is noted that the same reference numerals of letter will be used to designate like or equivalent elements having the same function.

Further, in the following description, numeral specific details such as concrete components comprising the circuit and the frequency, are set forth to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practised without these specific details. The detailed description of known function and constructions that unnecessarily obscure the subject matter of the present invention will be avoided in the present description.

Note that the later referred to terms are defined considering the functions in the present invention which can be varied according to the intention of the designer or according to practice. The terms employed in the present specification are as follows: "DI" and "DO" signify input data and output data each having the 8-bit or 16-bit data width, respectively; "DBI" and "DBO" signify the input data and output data of a buffer, respectively; "MOD" is a mode control signal externally provided, e.g., from a central processing unit and can be varied according to a size of the input data and output data; "Wptr" signifies a write pointer and the input data is written on a storing area of the buffer indicated by the write pointer; "Rptr" signifies a read pointer and the data written on the storing area of the buffer indicated by the read pointer is outputted; "WEN" indicates a write enable signal provided for the writing operation from the exterior, and "REN" indicates a read enable signal provided for the reading operation; and "Full Flag" is a full flag indicating that data is written on all the area of the buffer, and "Empty Flag" is an empty flag indicating that no data is written on any area of the buffer.

The following description of the present invention will be based on an assumption that the size of the input/output data is 8 bits or 16 bits. In other words, the description will be made according to each case of: (1) 8-bit of the input data and the output data, (2) 8-bit of the input data and 16-bit of the output data, (3) 16bit of the input data and 8-bit of the output data and (4) 16-bit of the input and output data.

Figure 3 is a block diagram illustrating the structure of a first-in first-out memory device according to the present invention.

Referring now to Figure 3, a FIFO device according to the present invention comprises a data input unit 100, a buffer 200, a data output unit 300 and a pointer and flag generator 400. The configuration of the data input unit 100, the buffer 200, data output unit 300 and the pointer and flag generator 400 is shown in Figure 4 through 7, respectively.

Figure 4 is a detailed diagram illustrating the structure of the data input unit of Figure 3.

In Figure 4, the data input unit 100 performs multiplexing input data DI (DIH and DIL) having an 8 or 16 bits size according to an input mode control signal IMOD which is a sort of selection signal, to thereby output buffer input data DBIH and DBIL which are data strings each having an 8 bits size. The input mode control signal IMOD is a signal whose level is predetermined according to the size of the input data, by which the data input unit 100 performs a corresponding operation. When the size of the input data is 8 bits, the data input unit 100 outputs the input data DI (DIH and DIL) [0:7 as buffer input data DBIL [0:7] and DBIH [8:15]. Unlike the above case, when the size of the input data is 16 bits, the data input unit 100 outputs the input data DIL [0:7] and DIH [8:15] as buffer input data DBIL [0:7] and DBIH [8:15], respectively.

Figure 5 is a detailed diagram illustrating the structure of the buffer of Figure 3.

In Figure 5, the buffer 200 is comprised of preset storing areas, i.e., a register blockl 210 and a register block2 220 each having a 4-byte size. The buffer 200 stores the buffer input data DBI (DBIH and DBIL) output from the data input unit 100 in the area of the register blocks 210 and 220 indicated by the write pointer Wptr.

When the input data DBI (DBIH and DBIL) is 8 bits, the buffer 200 alternately writes the buffer input data DBIH [0:7] and DBIL [0:7] on the register blocks 210 and 220 according to the write pointer Wptr. For instance, when the buffer input data DBI (DBIH and DBIL) of 8 bytes is inputted by 8 bits and the data is DBI0, DBI1, ... and DBI8, DBIH is a data string of the DBIO, DBI2, .. and DBI8 and DBIL is a data string of the DBI1, DBI3, .. and DBI7. Thus, DBIH (DBI0, DBI2, DBI4 and DBI6) of 8-bit 4byte is written on the register blockl 210, and DBIL (DBI1, DBI3, DBI5 and DBI7) of 8-bit 4-byte is written on the register block2 220.However, when the input data DBI (DBIH and DBIL) is 16 bits, the buffer 200 concurrently writes the buffer input data DBIH [8:15] and DBIL [0:7] on the register blocks 210 and 220 according to the write pointer Wptr. For example, when the buffer input data DBI of 8 bytes is input by 16 bits, DBIH (DBI0, DBI1, DBI2 and DBI3) of 16-bit 4-byte is written on the register block 210, and DBIL (DBI0, DBI1, DBI2 and DBI3) of 16-bit 4-byte is written on the register block2 220.

Figure 6 is a detailed diagram illustrating the structure of the data output unit of Figure 3.

In Figure 6, the data output unit 300 reads as input data DBO the output data written on the area of the register block indicated by the read pointer Rptr and outputs output data DOH and DOL having a format suitable for the size indicated by an output mode control signal OMOD. The output mode control signal OMOD is a signal whose level is predetermined according to the size of the output data which is 8 bits or 16 bits. When the output mode control signal OMOD is 8 bits, the data output unit 300 only outputs output data DOL [0:7], and when 16 bits, the data output unit 300 outputs the output data DOL [0:7] and DOH [8:15].

Figure 7 is a detailed diagram illustrating the structure of the pointer and flag generator of Figure 3.

Referring to Figure 7, the pointer and flag generator 400 is composed of a write pointer generator 410, a read pointer generator 420 and a flag generator 430. The write pointer generator 410 generates a write pointer Wptr indicating the storing area of the buffer 200 where the buffer input data DBI is to be written, by using the write enable signal WEN and the input mode control signal IMOD applied from the exterior. The read pointer generator 420 generates a read pointer Rptr indicating the storing area of the buffer 200 where the data is to be read among the data written on the buffer 200, by using the read enable signal REN and the output mode control signal OMOD applied from the exterior.The flag generator 430 generates a full flag Full Flag and an empty flag Empty Flag which indicates how much data is written on the buffer 200, by using the write and read pointers Wptr and Rptr.

The operation of the FIFO device to output the output data having a size different from that of the input data, as illustrated in Figures 3 through 7 will now be described hereinafter.

Firstly, when the input data size is 8 bits and the output data size is 16 bits, i.e., when the size of the input data is larger than that of the output data, the operation of the FIFO device of the present invention will be described with reference to (A) to (E) of Figure 8.

In this case, since the size of the input data to be written is larger than that of the output data size to be read, the increment of the read pointer Rptr is made to be larger than that of the write pointer Wptr. The difference between the increments of the write pointer Wptr and the read pointer Rptr corresponds to the ratio of the size of the input data to the size of the output data. When there is no data written on the buffer 200 at the initial stage, the write pointer Wptr and read pointer Rptr indicate an address "000" of the buffer 200 as shown in (A) of Figure 8. In this situation, when the write enable signal WEN is applied, the write pointer generator 420 generates the write pointer Wptr. In (B) of Figure 8, the write pointer Wptr indicates an address "011." At this point, when the read enable signal REN is applied, the read pointer generator 420 generates the read pointer Rptr. Thus, data is written in the buffer 200 and the written data is read therein. When the data is written and read in a state as shown in (B) of Figure 8, the write pointer Wptr and the read pointer Rptr indicate addresses "110" and "100," respectively, after a predetermined time (after increasing pointers by 3 steps).At this time, the values of the write pointer Wptr and read pointer Rptr do not necessarily indicate the addresses "110" and "100." Instead, they may indicate addresses "101" and "100." In a state in which, as shown in (C) of Figure 8, the write pointer Wptr indicates an address "010" prior to the read pointer Rptr and then the read pointer Rptr indicates the address "010" (A in (D) of Figure 8) while the data write and read operations are concurrently performed as shown in (C) of Figure 8, the flag generator 430 generates an Empty Flag. The flag generator 430 generates the Empty Flag even when the write pointer Wptr and read pointer Rptr indicate the addresses "011" and "010," respectively (B in (D) of Figure 8). This is because the written data is 1 byte but the data to be read is 2 bytes in the latter case, i.e., upon generating the Empty Flag.That is, the total byte number to be written by 8 bits should be an even number. In a state in which the read pointer Rptr indicates an address "110" prior to the write pointer Wptr as shown in (E) of Figure 8 and then the write pointer Wptr also indicates the address "100" while the data write and read operations are concurrently performed as shown in (C) of Figure 8, the flag generator 430 generates an Full Flag. This is because the data is written in all the area of the buffer 200.

To sum up, the data having a size larger than that of the input data can be outputted by making the increment of the read pointer Rptr larger than that of the write pointer Wptr.

Next, when the input data size is 16 bits and the output data size is 8 bit, i.e., when the size of the input data is larger than that of the output data, the operation for performing the FIFO device according to the present invention will be described with referring Figure 9.

Since, in this case, the size of the input data to be written is larger than that of the output data to be read, the increment of the write pointer Wptr is made larger than that of the read pointer Rptr. The difference between the increments of the write pointer Wptr and the read pointer Rptr corresponds to the ratio of the size of the input data to the size of the output data. When there is no data written on the buffer 200 at the initial stage, the write pointer Wptr and read pointer Rptr indicate an address "000" of the buffer 200 as shown in (A) of Figure 9. In this situation, when the write enable signal WEN is applied, the write pointer generator 410 generates the write pointer Wptr. In (B) of Figure 9, the write pointer Wptr indicates an address "100." At this point, when the read enable signal REN is applied, the read pointer generator 420 generates the read pointer Rptr, too.Thus, data is written in the buffer 200 and the written data is read therein. When the data is written and read in a state as shown in (B) of Figure 9, the write pointer Wptr and the read pointer Rptr indicate addresses "110" and "010," respectively, after a predetermined time (after increasing pointers by 1 step).

In a state in which, as shown in (D) of Figure 9, the write pointer Wptr indicates an address "010" prior to the read pointer Rptr and then the read pointer Rptr indicates the address "010" while the data write and read operations are concurrently performed as shown in (C) of Figure 9, the flag generator 430 generates an Empty Flag. This is because the data written in the total area of the buffer 200 is read. In a state in which, as shown in (E) of Figure 9, the read pointer Rptr indicates an address "100" prior to the write pointer Wptr and then the write pointer Wptr also indicates the address "100" while the data write and read operations are concurrently performed as shown in (C) of Figure 9, the flag generator 430 generates an Full Flag.The flag generator 430 generates the Full Flag even when the read pointer Rptr indicates the address "010" and then indicates the address "101" by increasing the pointer value by 3 steps. This is because, though the area of the buffer 200 indicated by the write pointer Wptr is 1 byte smaller than that indicated by the read pointer Rptr, data of 1 byte is to be lost if such a state is not determined to be buffer full.

To sum up, data having a size smaller than that of the input data can be output by making the increment of the write pointer Wptr larger than that of the read pointer Rptr.

The operation according to the present invention can be also applied to a case in which the size of the input data and the size of the output data are congruous with each other. According to this case, the sizes of both the input data and the output data are 8 bits or 16 bits. Such a operation will be described referring to Figure 10 which shows a case in which the sizes of both the input data and output data are 8 bits.

According to this case, since the size of the input data to be written and the size of the output data to be read are congruous with each other, the increments of the write pointer Wptr and read pointer Rptr are the same as each other. When there is no data written on the buffer 200 at the initial stage, the write pointer Wptr and read pointer Rptr indicate an address "000" of the buffer 200 as shown in (A) of Figure 10. In this situation, when the write enable signal WEN is applied, the write pointer generator 410 generates the write pointer Wptr. In (B) of Figure 10, the write pointer Wptr indicates an address "011." At this point, when the read enable signal REN is applied, the read pointer generator 420 generates the read pointer Rptr. Thus, data is written in the buffer 200 and the written data is then read therein.Once the data is written and read in a state as shown in (B) of Figure 10, the write pointer Wptr and the read pointer Rptr indicate addresses "101" and "011," respectively, after a predetermined time (after increasing pointers by 2 steps).

In a state in which, as shown in (D) of Figure 10, the write pointer Wptr indicates an address "001" prior to the read pointer Rptr and then the read pointer Rptr indicates the address "001" while the data write and read operations are concurrently performed as shown in (C) of Figure 10, the flag generator 430 generates an Empty Flag.

This is because the data written in the total area of the buffer 200 is read. While the data write and read operations are concurrently being performed as shown in (E) of Figure 10, when the write pointer Wptr indicates an address "101" after the read pointer Rptr indicates the address "101", the flag generator 430 generates the Full Flag.

To sum up, the data having the same size as the input data can be output by making the increment of the write pointer Wptr and that of the read pointer Rptr congruous.

In the meantime, the flag generator 430 has a flag which is set as "1" when the write pointer Wptr indicates the address "111" and then the address "000" and cleared to "0" when the read pointer Rptr indicates the address "111" and then the address "000." In a case in which the addresses indicated by the write pointer Wptr and the read pointer Rptr are congruous with each other and the state of the flag is set as "0," the Empty Flag is generated. In a case in which the addresses indicated by the write pointer Wptr and the read pointer Rptr are congruous with each other and the state of the flag is set as "1," the Full Flag is generated.

As described above, it is a merit that the size of the input data and the size of the output data can be different from each other by differentiating the increment of the write pointer Wptr indicating an area to write the input data from that of the read pointer Rptr indicating an area to read the written data.

Meanwhile, it should be understood that the present invention is not limited to the particular embodiment disclosed herein as the best mode contemplated for carrying out the present invention, but rather that the present invention is not limited to the specific embodiments described in this specification except as defined in the appended claims. That is, for instance, though the size of the input/output data is exampled to be 8 bits or 16 bits in the present description, 32 bits can be also applied to the present invention. Such a case can be possible by configuring the buffer with four register blocks and properly selecting the ratio of the increments of the write pointer Wptr and the read pointer Rptr according to the ratio of the input data to the output data.

While there have been illustrated and described what are considered to be preferred embodiments of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made, and equivalents made be substituted for elements thereof without departing from the true scope of the present invention. In addition, many modifications may be made to adapt a particular situation to the teaching of the present invention without departing from the central scope thereof. Therefore, it is intended that the present invention not be limited to the particular embodiments disclosed as the best mode contemplated for carrying out the present invention, but that the present invention includes all embodiments falling within the scope of the appended claims.

The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

All of the features disclosed in this specification (including any accompanying claims, abstract and drawings) , and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) , may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings) , or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

Claims

1. A first-in first-out memory device, comprising: a data input unit for outputting input data as a plurality of data strings having a preset size in correspondence with an external mode control signal determined by the size of the input data and the output data; a pointer generating unit for generating a write pointer and a read pointer in correspondence with said mode control signal; a buffering unit composed of a plurality of register blocks having a preset storage area, for concurrently or alternately writing the plurality of data strings outputted from said data input unit on the storage area of each of said register blocks indicated by said generated write pointer;; a data output unit for concurrently or alternately reading the data written on each register block of said buffering unit in correspondence with said read pointer, to thereby output as output data having a format corresponding to said mode control signal; and a flag generating unit for generating a flag indicating the amount of the data written on said buffering unit by using said write pointer and said read pointer.

2. A first-in first-out memory device as claimed in claim 1, wherein said data input unit repeatedly outputs the data string having a size of said input data until the size becomes congruous with that of said output data when said mode control signal indicates that the size of said output data is larger than that of said input data size.

3. A first-in first-out memory device as claimed in claim 1 or claim 2, wherein said pointer generating unit generates a write pointer having an increment corresponding to said mode control signal and a read pointer having an increment larger than that of said generated write pointer.

4. A first-in first-out memory device as claimed in claim 3, wherein the increment of said read pointer is as large as the ratio of the size of said input data to the size of said output data, rather than the increment of said write pointer.

5. A first-in first-out memory device as claimed in any preceding claim, wherein said buffering unit has a plurality of register blocks having the storage area same as the size of the input data and said data string is alternately written on each register block corresponding to said generated write pointer.

6. A first-in first-out memory device as claimed in any preceding claim, wherein said data output unit alternately reads the data written on each register block of said buffering unit corresponding to said read pointer and then outputs the read data as output data having a format corresponding to said mode control signal.

7. A first-in first-out memory device as claimed in claim 1 or claim 2, wherein when said mode control signal indicates that the size of the input data is larger than that of the output data, said data input unit divides the input data into a plurality of data strings having the size of said output data, to thereby output the divided input data.

8. A first-in first-out memory device as claimed in claim 7, wherein said pointer generating unit generates a write pointer having an increment corresponding to said mode control signal and a read pointer having an increment less than that of the generated write pointer.

9. A first-in first-out memory device as claimed in claim 8, wherein the increment of said read pointer is as small as the ratio of the size of said input data and the size of said output data rather than the increment of said write pointer.

10. A first-in first-out memory device as claimed in any one of claims 7-9, wherein said buffering unit has a plurality of register blocks having the storage area same as the size of the output data and said data string is concurrently written on each register block corresponding to said generated write pointer.

11. A first-in first-out memory device as claimed in any one of claims 7-10, wherein said data output unit concurrently reads the data written on each register block of said buffering unit corresponding to said read pointer and then outputs the read data as output data having a format corresponding to said mode control signal.

12. A method for processing input/output data of a firstin first-out memory device which performs data writing and reading operations by using a write pointer and a read pointer, said method comprising the steps of: generating a write pointer having a preset increment and a read pointer having an increment larger than that of said write pointer when the size of output data to be read is larger than that of input data to be written; writing said input data on said first-in first-out memory by using said generated write pointer; and reading said input data written on said first-in first-out memory by using said generated read pointer, to thereby output the read input data as output data.

13. A method as claimed in claim 11, wherein the increment of said read pointer is as large as the ratio of the size of said input data and the size of said output data rather than the increment of said write pointer.

14. A method for processing input/output data of a firstin first-out memory device which performs data writing and reading operations by using a write pointer and a read pointer, said method comprising the steps of: generating a write pointer having a preset increment and a read pointer having an increment less than that of said write pointer when the size of input data to be written is larger than that of output data to be read; writing said input data on said first-in first-out memory by using said generated write pointer; and reading said input data written on said first-in first-out memory by using said generated read pointer, to thereby output the read input data as output data.

15. A method as claimed in claim 14, wherein the increment of said write pointer is as large as the ratio of the size of said input data and the size of said output data rather than the increment of said read pointer.

16. A first-in first-out memory device which generates a write pointer having a preset increment and a read pointer having an increment larger or smaller than the write pointer when the size of output data to be read is different from that of input data to be written, writes the input data on the first-in first-out memory by using the generated write pointer, and reads the input data written on the first-in first-out memory by using the generated read pointer, to thereby output the read input data as output data.

17. A first-in first-out memory device according to claim 16, in which the first-in first-out memory generates a write pointer having a preset increment and a read pointer having an increment larger than that of the write pointer when the size of output data to be read is larger than that of input data to be written.

18. A first-in first-out memory device according to claim 16, in which the first-in first-out memory generates a read pointer having a preset increment and a write pointer having an increment larger than that of the read pointer when the size of output data to be read is smaller than that of input data to be written. At this stage, the increment of the write pointer is as large as the ratio of the size of the input data and the size of the output data rather than the increment of the read pointer.

19. A first-in first-out memory device, comprising a storage area and means for adaptively inputting and outputting data according to the size of the input and output data respectively.

20. A first in first-out memory device according to claim 19, further comprising any one or more of the features of the accompanying description, claims, abstract and/or drawings, in any combination.

21. A first in first-out memory device substantially as described herein, with reference to and as shown in Figures 3-7 of the accompanying drawings.

22. A method for processing input/output data of a firstin first-out memory, which method is substantially as described herein.