JPH0479422A - Transmission control circuit - Google Patents

Abstract

PURPOSE:To increase the operation speed by providing first and second data buffer circuits, selecting these circuits to read out stored parallel data and converting it to a serial data. CONSTITUTION:An address control buffer circuit 1 including a first end bit register which performs the read operation synchronously with a first data register 11A and a data buffer circuit 2 including a second end bit register 13 which performs the read operation synchronously with a first data register 11B are provided. A parallel/serial converting circuit 5 or the like is provided which successively converts parallel data read out from circuits 1 and 2 to serial data DTS in accordance with a flag synchronizing signal FS to send this data DTS and outputs a read signal RD. Thus, plural frames are continuously transmitted without issuing a transmission request to a host system at each time of one frame, and the operation speed is increased and the execution efficiency of the host system is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a transmission control circuit, and more particularly to a transmission control circuit that converts parallel data input in parallel into predetermined serial data and outputs the same.

[Conventional technology]

Conventionally, defined communication protocols, such as HDL C (
High Level Data Link Cont
The frame format according to the ROL Procedure includes multiple data fields, namely an address field, a control field, a conveyance information field,
and Fe2(Frame Checking Sequence
One frame consists of four fields: nce) field.

As a conventional transmission control circuit for converting parallel data into HDLC serial data and transmitting it from the host system, there is a circuit as shown in FIG.

This circuit uses parallel data DTP sent in parallel.
is converted into an HDLC serial frame format and transmitted using the following procedure.

First, when it becomes possible to transmit, it enters an idle transmission mode and the flag generation circuit 3 sends out a flag pattern FP. In this state, the parallel data D of the first transmission data
This continues until the TP is transferred from the post system to the transmit buffer circuit 7. Typically, the transmission buffer circuit 7 has an FTFO configuration of several stages to several tens of stages. The main features of the transmission buffer circuit 7 are data registers 1 and 1, which are equipped with n-bit registers for storing parallel data DTP.
Use pins 1 to 12 with bit registers
and an end bit register 13 having registers of 1 bit 1 to 1.

The special register of the use bit register 12 indicates that valid parallel data DTP is present in the corresponding stage of the data register 11 5, and the register of the end pit register 13
indicates the position of the fif& parallel data of one transmission frame among the parallel data existing in the data register 11.

The host register is the use bit register 12 at the write end.
After confirming that the register is at the reset level, parallel data DTP is written to data register 1].

When the parallel data DTP is transferred to the transmission buffer circuit 7, the parallel-to-serial conversion circuit 5 sends a read signal RD to the transmission buffer circuit 7 in response to the flag synchronization signal FS from the flag generation circuit 3. The parallel data read out from the transmission buffer circuit 7 by the read signal RD is sent to the parallel/serial conversion circuit 5, where it is converted into serial data DTS and sent out.

When the parallel-to-serial conversion circuit 5 reads out the parallel data at the set level of the end pit register 13 from the data register 11, it converts it into serial data DTS and sends it out, and ends the parallel-to-serial conversion operation.

In the HDLC frame format, the FC8 generation circuit sends out the FCS field following the last serial data from the parallel-to-serial conversion circuit 5, and the flag generation circuit 3 sends out the flag pattern FP to complete one frame. Complete the send operation.

[Problem to be solved by the invention]

The conventional transmission control circuit described above has a configuration in which all the parallel data of one frame is stored in the same transmission buffer circuit 7, so that the host system stores address data of one frame in the transmission buffer circuit 7, When writing control data and transferring subsequent transmission information from an external storage device to the transmission buffer circuit 7 by DMA transfer,
After all the parallel data of one frame has been transferred to the transmission buffer circuit 7, unless the transmission buffer circuit 7 becomes ready for writing, the parallel data of the next frame cannot be transferred. For each parallel data transfer, address data and control data must be written from the host system, and then the transmission information must be transferred via DMA from an external storage device, which has the disadvantage of not being able to operate at high speed. Each time a message is transmitted, a transmission request is issued to the host system, and the host system processes the request, which has the disadvantage that the execution efficiency of the host system also decreases.

An object of the present invention is to be able to transmit multiple frames in succession without issuing a transmission request to the host system for each frame, thereby speeding up the operation and improving the execution efficiency of the host system. The purpose of this invention is to provide a transmission control circuit that can

[Means to solve the problem]

The transmission control circuit of the present invention includes a plurality of first n-bit registers that sequentially store a plurality of units of first data in n-bit units input in parallel, and the data is stored in accordance with a selection signal and a read signal. A first data buffer circuit includes a FIFO-type first data register that reads data in n-bit units in parallel, and a plurality of second data registers that sequentially store plural units of n-bit second data input in parallel. A FIFO-type second data register comprising n-bit registers and reading stored data in n-bit units in parallel according to the selection signal and readout signal, and corresponds to each of the second n-bit registers. and a 1-bit register provided in the second n-bit register, and when the data stored in the second n-bit register is the final data of one frame, the 1-bit register corresponding to the second n-bit register is provided. a second data buffer circuit including an end bit register that sets the register to a set level and reads stored data in synchronization with the read operation of the second data register; a counter circuit that outputs the selection signal that inputs the read data and puts one of the first and second data buffer circuits into a read operation state; and The parallel/serial conversion circuit sequentially converts the data into serial data and outputs the serial data.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In this embodiment, n bits of atto 1 are input in parallel.
A PIFO-type first data register that includes a plurality of n-bit registers that sequentially store a plurality of units of /space data and control data, and that reads stored data in n-bit units in parallel according to a selection signal BS and a read signal RD. 11A
, a first 1-bit register provided corresponding to each n-bit register of the first data register IIA, and a register for the corresponding n-bit 1 of the 11 first data registers. A first use bit register 12A and a first data register that set a corresponding first 1-bit register to a set level when valid parallel data exists and perform a read operation in synchronization with the first data register 11Δ; A second 1-bit register is provided corresponding to each n-bit register of the IIA, and the parallel data of the corresponding n-bit register of the first data register 11A is stored in one file I/A.
- A first end pit register that sets the corresponding second 1-bit register to the set level and performs a read operation in synchronization with the first data register 11A when the data is parallel data of a frame division or one transmission division. 13A, and a plurality of n-bit registers that sequentially store a plurality of n-bit transmission information input in parallel, and data stored in accordance with a selection signal BS and a read signal RD. FIFO-type second data register 11 that reads data in n-bit units in parallel.
n, a third 1-bit register provided corresponding to each n-bit register of this second data register 11B, and a third 1-bit register that is valid for the corresponding n-bit register of this second data register 11B. When parallel data exists, the corresponding third 1-bit register is set to
・A second use bit register 12B that performs a read operation in synchronization with the second data register 1] and B.
, and a fourth 1-bit register provided corresponding to each n-bit register of the second data register 11B, and the parallel data of the corresponding n-bit register of the second data register 11B is 1. When it is the final parallel data of one frame, the corresponding fourth 1-bit register is set to the set level, and the data register including the second end pit register 13a performs a read operation in synchronization with the second data register 11B. F circuit 2
Then, when the state becomes ready for transmission, a flag generation circuit 3 outputs a flag synchronization signal FS and sends out flag patterns until the first parallel data DTP is transferred to the address/control buffer circuit 1. - A parallel/serial conversion circuit 5 that sequentially converts the parallel data read from the control buffer circuit 1 and the data buffer circuit 2 into serial data DTS and sends it out, and also outputs a read signal RD; A selection signal BS that starts counting the read signal RD from the conversion circuit 5 and puts either the address/control buffer circuit 1 or the data buffer circuit 2 into a read operation state according to this count value.
and a counter circuit 6 which resets the count value and starts counting the read signal RD again when the set level data is input from the end pit register 13B of the data buffer circuit 2, and The configuration includes an FC8 generation circuit 4 that inserts an FCS frame.

Next, the operation of this embodiment will be explained.

First, when it becomes ready for transmission, it enters an idle transmission mode, and the flag generation circuit 3 sends out a flag pattern FP. This state continues until the parallel data I)TP of the first transmission data is transferred from the host system to the address control buffer circuit 1.

Parallel data D transferred from the host system, etc.
TP or address data, if it is control data, address/
data register of control buffer circuit 1], IA, and when it is transmission information, it is stored in data register 11B of data buffer circuit 2.

When confirming that parallel data is stored in the address/control buffer circuit 1 or data buffer circuit 2 selected by the selection signal BS, the parallel/serial conversion circuit 5 converts the data according to the flag synchronization signal FS from the flag generation circuit 3. Address/control buffer circuit 1. Read signal RD to data buffer circuit 2 and counter circuit 6
send.

When the counter circuit 6 becomes ready for transmission, it starts counting the read signal RD from the parallel-serial conversion circuit 5. The selection signal BS is controlled according to the count number to select the read destination of the parallel data. In other words, in the HDLC protocol, the first and second bytes are address data,
Since it is control data, the address/control buffer circuit 1
If it is the third byte or later, it is determined to be transmission information and the data buffer circuit 2 is selected.

Therefore, when transmission starts, the address/control buffer circuit 1 is first selected by the selection signal BS.

The parallel data read from the address/control buffer circuit 1 is sent to the parallel/serial conversion circuit 5, where it is converted into n-bit long serial data DTS and sent out. When parallel data is subsequently read from the address/control buffer circuit 1, the selection signal BS selects the data buffer circuit 2. That is, the parallel data starting from the third byte of one frame is read from the data buffer circuit 2.

and the end pit register of data buffer circuit 2]
, ], When the cent level data is sent out from n, the parallel data in the corresponding data register IIB is converted into serial data DTS and sent out.
The operation of converting one frame of parallel data into serial data is completed. At the same time, the counter circuit 6 is also reset, and the selection signal BS selects the address/control buffer circuit 1 again. However, in the HDLC frame format, the last converted serial data DTS is followed by the FCS from the FC8 generation circuit 4. The field is sent out, and the flag pattern FP is sent out from the flag generation circuit 3.
Complete the frame transmission operation.

In this embodiment, even before the address data and control data of the first frame are sent, the data register of the address/control buffer circuit 1 and the write end side of the IA are vacant, so the second frame is It is possible to transfer frame address data and control data to the address/control buffer circuit 1. Furthermore, even if the transmission information of the second frame is transferred to the data buffer circuit 2 by DMA transfer using a chain function or the like before the transmission of the first frame is completed, the transmission information of the second frame is transferred to the data buffer circuit 2 by the selection signal BS. The address data and control data can be stored in the data buffer circuit 2 until they are sent, and can be sent out following the second address data and control data.

In this way, if the parallel data of the next frame has already been written to the address/control buffer circuit 1 and the data buffer circuit 2, the system can be sent to the host 1 after the transmission of the first frame is completed. It is possible to transmit the second frame in succession without any delay.

Furthermore, if there is space in the address/control buffer circuit 1 or the data buffer circuit 2, it is also possible to store the parallel data of the next frame.

In FIG. 2, when the parallel/serial converter i/+ 5 is reading the address data and control data of the first frame from the address/control buffer circuit 1 for three frames, each frame In Figure 2, IF,
2F and 3F) are shown.

The address/control buffer circuit 1 receives the address/address data and control data of the second and third frames (2F, 3F"), and the data buffer circuit 2 receives the first frame transmission information. It is also stored without being sent.

All parallel data in the data buffer circuit 2 is DMA transferred from the external storage device OO.

The transmission information of the second and third frames has not yet been transferred to the data buffer circuit 2.

As described above, in this embodiment, the address data and control data of each frame are divided and stored in the address/control buffer circuit 1, and the transmission information is stored in the data buffer circuit 2. Therefore, when transmitting multiple frames, Since the parallel data of each frame can be written in advance without issuing a transmission request to the post system for each frame, continuous transmission is possible without the intervention of the host system.

FIG. 3 is a block diagram showing a second embodiment of the invention.

Normally, in the HDLC protocol, a frame with an address field of 1 byte length and a control field of 1 byte length is defined as a valid frame according to the standard, but in address extension mode, the address field is 2 bytes valid, and If modulo 128 is used, the control field is expanded to 2 bytes. Therefore, the address field and control field in the HDLC protocol are 2~
Can be expanded to 4 bytes.

Therefore, in this embodiment, it is possible to deal with such address fields and control fields, and the counter circuit 6A is controlled by the address/control buffer circuit 1i'i) by the selection column I/value program signal CP.
The count value for selecting the read operation of the data buffer circuit 1 and the data buffer circuit 2 can be changed.

Other basic operations and effects are the same as in the first embodiment.

〔Effect of the invention〕

As explained above, the present invention includes a first data buffer circuit that stores address data and control data of input parallel data, and a second data buffer circuit that stores transmission information of input parallel data. By selecting these data buffer circuits to read out the stored parallel data and convert it into serial data, data can be transmitted continuously without having to issue a transmission request to the host system for each frame. It is possible to transmit a plurality of frames, thereby increasing the speed of operation and improving the execution efficiency of the host system.

[Brief explanation of drawings]

]7 FIGS. 1 and 2 are a block diagram of a first embodiment of the present invention and a block diagram showing the flow of parallel data for explaining the operation of this embodiment, and FIG. 3 is a block diagram of a first embodiment of the present invention. FIG. 4 is a block diagram showing an example of a conventional transmission control device. 1...Address/control buffer circuit, 2...Data buffer circuit, 3...Flag generation circuit, 4...F
CS generation circuit, 5...Parallel/serial conversion circuit, 6
．． 6A...Counter circuit, 7...Transmission buffer circuit, 11.1. LA, IIB...data register, 12
．． 12A, 12B...Use bit register, 13.
13A, 13B... End pit register, 100.
...External storage device.

Claims (1)

[Claims] It is equipped with a plurality of first n-bit registers that sequentially store plural units of first data in n-bit units that are input in parallel, and stores stored data in parallel in n-bit units according to a selection signal and a read signal. a first data buffer circuit including a FIFO-type first data register for reading data; and a plurality of second n-bit registers for sequentially storing plural units of n-bit second data input in parallel. a FIFO-type second data register for reading stored data in n-bit units in parallel according to the selection signal and the readout signal; A bit register is provided, and the data stored in the second n-bit register is 1.
When the data is the final data of one frame, the 1-bit register corresponding to the second n-bit register is set to the set level and the stored data is read out in synchronization with the read operation of the second data register. a second data buffer circuit including a bit register; and inputting the read signal and the read data of the end bit register to put one of the first and second data buffer circuits into a read operation state. A transmission control circuit comprising: a counter circuit that outputs a selection signal; and a parallel/serial conversion circuit that sequentially converts data read from the first and second data registers into serial data and outputs the serial data.