JPS6010344B2 - Input/output data transfer method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for transferring input/output data between a channel and an input/output control device.

Conventionally, a low-speed input/output device is connected to a byte multiplexer channel of a processing unit and transfer processing is performed in units of bytes, and memory access is performed each time, reducing the efficiency of the processing unit. In particular, in input/output devices with fixed data lengths such as card leagues, mark sheet readers, and line printers, non-necessary data is often a series of specific unnecessary codes. However, if a similar data transfer is performed and the processing response is not received in time, an error occurs, resulting in unnecessary error recovery processing. Normally, in order to increase the efficiency of input/output data transfer, methods such as reducing the number of memory accesses by providing data buffers and measures to prevent processing unresponsiveness are taken, but byte multiplexer channels process in units of 1/byte. This kind of countermeasure is not normally taken because of the idea that this method will be used, and if this method were to be implemented, the amount of hardware required for the data buffer would be enormous, making it impossible to implement.

An object of the present invention is to reduce the number of memory accesses for transferred data without providing a data buffer, and to increase the allowable processing non-response time, thereby improving the efficiency of a processing device.

Therefore, in the present invention, when the data to be transferred is the same,
It is characterized by processing the number of bytes equivalent to memory access (for example, up to 4 bytes) with a 1-byte transfer.
This makes it possible to reduce the number of memory accesses and extend the allowable time for processing non-response.

Hereinafter, the present invention will be explained in detail with reference to Examples. The figure shows an embodiment of the present invention, where A is the channel side and B is the input/output control device side.

In the figure, channel A is connected to a memory 100 through a memory register 1, and to an input/output control device through an input data register 2 and an output data register 3. For convenience, it is assumed that the memory 100 can read and write a maximum of 4 bytes of data in one memory cycle. Therefore, memory register 1 has a 4-byte structure. Both the input data register 2 and the output data register 3 have a 1-byte structure, and input or output data is transferred to and from the memory register 1 or the input/output control device B in units of 1 byte. 4 is a byte control unit that controls which byte position in memory register 1 the data of input data register 2 is stored;
This is a data comparison unit that compares the data at each byte position read from 00 to the memory register 1 and notifies the byte control unit 4 of the result.

On the other hand, the input/output control device B has a data buffer register 6 with a 1-byte structure, and data read from the input/output device is transferred via the buffer register 6 in units of 1 byte to the input data register 2 on the channel side. Further, the contents of the output data register 3 on the channel side are transferred to the input/output device.

7 is a flip-flop that indicates whether data read from the input/output device is in the buffer register 6;
8 is a comparison gate circuit that compares the data in the buffer register 6 and the discussion data from the next input/output device to see if they are the same.

9 is a counter that counts how many bytes of data following the data stored in the buffer register 6 are the same.

The counter 9 is a binary reversible counter with a 2-bit structure, and counts up by the output of the gate G7 and counts down by the output of the gate G9, so that it can count up to 3 bytes of the same data. 10 is a delay circuit.

Note that R is a signal that becomes logic "1" when reading data from the input/output device (that is, during a read command operation), and W becomes a logic "1" when writing data to the input/output device (that is, during a write command operation). signal, T is a signal that specifies the data discussion timing, T' is a signal that specifies the data sending timing, STR is a signal that transfers 1 byte of data from the input/output control device to the channel, and when it is received by the channel, the channel It is a signal emitted from First, the case of receiving data from an input/output device will be explained. When one byte of data taken from the input/output device is stored in the data buffer register 6, input/output control device B issues a transfer processing request to the channel (the configuration required for this is omitted), and If the channel responds to the input data register 2 of channel A, the input data register 2 of channel A
Thereafter, it is transferred to the desired byte position of the memory register 1 indicated by the byte control unit 4, and stored in the memory 10 in a memory cycle. However, after the discussion data is stored in the buffer register 6, if the channel cannot respond to it and the transfer process is forced to wait, the data that is subsequently taken from the input/output device will be stored in the buffer register 6 because the buffer register 6 is not free. It will no longer be possible to store it. At this time, no STR signal arrives from the channel, and the flip-flop 7 remains set. When the flip-flop is in the set state, at the next discussion timing, the comparison gate circuit 4 compares the data stored in the buffer register 6 with the data subsequently retrieved from the input/output device, and if they match, If not, a processing non-response error is generated through OR gate G,3. On the other hand, if both data match, the counter 9 is incremented by 1 through the OR gate G7, and it is stored that there is 1 subsequent byte of data identical to the contents of the buffer register 6. The state of waiting for processing continues, and if the transaction data is generated during that time, the same operation is repeated, and if it is the same data as the buffer register 6,
Each time, the counter 9 is counted up and the number of bytes is stored. In this way, the counter 9 becomes "3".
In other words, if the count is counted up to the maximum number of bytes that can be processed in one memory cycle, and the same data continues to be taken after exceeding this, the AND condition of AND gate G, 2 is satisfied, and it is the same as in the case of mismatch. A processing non-response error is issued. In other words, even the buffer register 6 for 1 byte has a buffer function for up to 4 bytes in the case where the same data is consecutive.
The allowable processing non-response time increases accordingly. On the other hand, when the channel receiving the transfer request meets the response conditions, it takes in the contents of the buffer register 6 into the input data register 2 and issues an STR signal.

The flip-flop 7 is reset by this STR signal, and the input/output control device returns to normal operation. On the channel side, the contents of the input data register 2 are stored in the corresponding byte position of the memory register 1 indicated by the byte control unit 4 through a selected gate among the gates Go to G3 (for convenience, this gate is referred to as Go). be done. At this time, when the counter 9 counts up to a certain value and the output signal line b of the AND gate G is in the ``1'' state, the byte control unit 4 sends a clock to the signal line a at a constant timing. This clock is applied to the counter 9 through the AND gate G8 and the OR gate G9, and the contents of the counter 9 count down sequentially.During this time, the byte control section 4 operates the gates G, , , , , , , , , , , , , , , , , , , , , , in synchronization with the above-mentioned clock. G
2, . . . are sequentially selected, and the contents of input data register 2 are stored in byte positions 1, 2, . . . following byte position 0 of memory register 1. This operation is repeated until the contents of the counter 9 become "0" and the signal line b becomes "0". In other words, if the same data is sent successively from the I/O device, only 1 byte of data is transferred from the I/O control device to the channel, and up to 4
Bytes of the same data can be transferred to each byte location of the memory register 1. The data stored in the memory register 1 in this manner is then simultaneously written to the memory 100 at a maximum of 4 bytes in one memory cycle. Next, a case in which data is sent to an input/output device will be explained.

In this case, 4 bytes of data are extracted from the memory 100 in one memory cycle and stored in each byte position of the memory register, of which, for example, data at the 0 byte position is first transferred to the output data register 3. When the input/output control device receives a data transfer request from the channel, it takes in the data in the output data register 3 into the buffer register 6 through the AND gate G5, and sends it to the input/output device through an output data bus (not shown). On the other hand, the data comparison unit 5 on the channel side sequentially compares whether the data in the 1st to 3rd byte positions of the memory register is the same as the data in the 0th byte position, and stores the same data in the byte position following the 0th byte position. If there is an evening, the number of bytes is sent to the byte control unit 4.
Notify.

Assume now that the data in the 1st to 3rd byte positions of memory register 1 are all the same as the data in the 0th byte position. In this case, the data comparison unit 5 determines that the number of bytes of the same data is "3".
In response to this, the byte control unit 4 successively outputs three clocks to the signal line a. This clock is AND gate G6, OR gate G
7 to the counter 9, and the counter 9 reads "3".
will be counted up. As the counter 9 counts up, continuous output permission is issued through the AND gates G and 4. As a result, the input/output control device successively sends the data stored in the buffer register 6 to the input/output device at the timing of the T signal. During this time, no data is transferred from the memory register 1 to the output data register 3 on the channel side, and therefore no data transfer request is issued to the input/output control device. The above T' signal is the OR gate G9
The counter 9 counts down each time the same data in the buffer register 6 is sent to the input/output device. In this way, when the same data for the number of bytes set in the counter 9 is sent out, the counter 9 becomes "0", gates G and 4 are turned off, and the operation ends. Even in this case, a maximum of 4 bytes of data can be transferred in one memory cycle, and processing efficiency can be improved. As is clear from the above description, the following effects can be obtained according to the present invention.

1. The number of memory accesses of the processing unit is reduced, improving efficiency and improving performance.

2. The allowable processing non-response time can be expanded and processing non-response errors can be reduced.

[Brief explanation of the drawing]

The figure is a block diagram of one embodiment of the present invention. A... Channel side, B... Input/output control device side, 1... Memory register, 2... Input data register, 3... Output data register, 4... Byte control unit, 5
...Data comparison unit, 6...Data buffer register, 7...Flip-flop, 8...Comparison gate circuit, 9...Counter, 10...Delay circuit , 100...memory.

Claims (1)

[Claims] 1 Data transfer between the channel and the input/output control device
In a system configuration in which data is read in bytes, when the other device is unable to respond to data read from memory or an input/output device and is waiting for transfer, when the next data is read, the data becomes the data waiting to be transferred. Check if they are the same, and if they are the same, when the transfer queue is released,
An input/output data transfer method characterized by continuously transferring the previous data to the other device.