JP2669028B2 - Command register circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A programmable command register circuit which can arbitrarily write a command without reading the status of the processing circuit in response to a command from a central processing unit. A central processing unit that sends data and a write signal corresponding to a command with the aim of reducing the load on the central processing unit by reducing the interruption time that occurs between the end of writing and the next write. And the processing circuit having a plurality of first processing units to n-th processing units that operate according to the activation from the central processing unit and execute the processing of the command, delay the initial signal in the write signal. A delay unit for storing the data and corresponding to the output of the delay unit and the processing results of the plurality of first to n-th processing units; Based on the output,
A first first-in first-out memory that outputs a start command to the plurality of first processing units to the n-th processing unit, and a status of the start command from the plurality of first processing units to the n-th processing unit to the central processing unit And a second first-in first-out memory for sequentially operating the plurality of first processing units to n-th processing units sequentially from the central processing unit, and ending from a certain k-th processing unit. It is configured so that the next (k + 1) th processing unit can be activated without waiting for the status.

[Industrial applications]

The present invention relates to a programmable command register circuit in which a command can be arbitrarily written without reading the status of a processing circuit for a command from a central processing unit.

2. Description of the Related Art In recent years, a system for a central processing unit (hereinafter, referred to as a CPU) has been required to have a higher speed. For this reason, it is necessary for the CPU to reduce the software load on software related to the status of the processing circuit that processes the command output by the CPU, thereby increasing the speed.

[Conventional technology]

FIG. 4 is a diagram showing a circuit configuration of a conventional example. In the figure, 51
Is a central processing unit (hereinafter referred to as CPU) that controls the system, 52
Reference numeral denotes a data bus serving as a data path from or to the CPU 51, reference numeral 53 denotes a command register formed of a flip-flop (hereinafter, referred to as FF), and reference numeral denotes a processing circuit for processing a command sent from the CPU. FIG. 5 is a diagram showing a time chart of the conventional example.

The CPU 51 outputs both the data corresponding to the command 1 in FIG. 5 (b) and the write pulse signal in FIG. 5 (a) through the data bus 52, and the write is performed during the write cycle shown in FIG. 5 (f). When the pulse (a) is input,
At the rising timing t ₀ of the write pulse (a), the data (b) is latched, the data (b) to be output corresponding to the command 1 is started to be written in the command register 53, and the written data is the command 1 Is passed to the processing circuit 54 for processing.

Next, the processing circuit 54 confirms at the timing t ₁ that the processing of the data (b) corresponding to the command 1 has all been completed, and from “Low” to “Hig” shown in FIG. 5 (e).
It sends an interrupt signal to h'to the CPU 51. Receiving this interrupt signal, the CPU 51 recognizes that the processing circuit 54 has completed the correct command processing and is ready for reading, and at timing t ₂ , it outputs the reading pulse shown in FIG. 5 (c). In addition to the processing circuit 54, the reading of the data corresponding to the command 1 of FIG. 5 (b), which is input to the processing circuit 54 in the previous write cycle and processed, is started, and the reading is performed at the timing t ₃ . The operation of terminating the processing is performed, and the status shown in FIG. 5D indicating the processing status input to the processing circuit 54 is read out and input to the CPU 54.

Then, the CPU 51 confirms the confirmation cycle t _{3 for} a certain period of time until the data (b) corresponding to the next command 2 is input after the reading of the status shown in FIG. 5D is completed. After passing through the t _4, it starts writing data again corresponding to the next command 2 at a timing t ₅ the next pulse is inputted.

[Problems to be solved by the invention]

Therefore, the CPU cannot write a new next command until the status read confirmation cycle after the writing is completed, which causes a problem that a temporary interruption time does not occur in the operation of the processing circuit.

SUMMARY OF THE INVENTION It is an object of the present invention to reduce the interruption time that occurs during the time when the processing circuit completes one write and moves to the next write.

[Means for solving the problem]

The present invention, as shown in FIG. 1 and FIG. 2, operates by a central processing unit 1 that sends out data and a write signal corresponding to a command, and starts up from the central processing unit 1 to execute the processing of the command. Multiple first processing units 6
-1 to the processing circuit 6 having the n-th processing unit 6-n,
Delay means 4 for delaying an initial signal in the write signal
And storing the data, and based on the output of the delay unit 4 and the output corresponding to the processing results of the plurality of first processing units 6-1 to 6-n, the plurality of first processings. Part 6-1
A first-in first-out memory 3 for outputting a start command to the n-th processing unit 6-n;
A second first-in first-out memory 5 for notifying the central processing unit 1 of the status in response to the activation command from the n-th processing unit 6-n is provided, and the plurality of first processing units 6-1 to 6-n are connected. The order of sequential operation is set continuously from the central processing unit 1, and the next (k + 1) th processing unit 6- (k + 1) without having an end status from a certain kth processing unit 6-k. Configure so that it can be started.

(Operation)

In the present invention, as shown in FIG. 1, after data input from the central processing unit 1 via the data bus 2 is continuously written into the first first-in first-out memory 3 using a write pulse, the write pulse is delayed. The output data obtained by performing the first reading by applying the read pulse generated by the means 4 to the first first-in first-out memory 3 is input to the processing circuit 6 for processing, and output from the processing circuit 6. The read pulses to be read out are sequentially applied to the first first-in first-out memory 3 so that the second and subsequent readings from the first first-in-first-out memory 3 are sequentially performed, and the other output from the processing circuit 6 is output. The status is added to the second first-in first-out memory 5 and the read pulse output from the processing circuit 6 is used as a write pulse. To perform the writing to the second FIFO 5 of status.

Therefore, since the central processing unit 1 can write the data corresponding to an arbitrary command without being involved in the reading of the status of the processing circuit 6, the time for the central processing unit 1 to read the status and the end recognition time can be reduced. Since the number can be reduced, it is possible to speed up the central processing unit 1 and reduce the load on software.

〔Example〕

FIG. 2 is a diagram showing a circuit configuration of one embodiment of the present invention. In the figure, 6 is a processing circuit including a first processing unit 61 to an eighth processing unit 68. When the data corresponding to an input command has an 8-bit structure, the first processing unit 61 uses the first data of the first data.
The eighth processing unit 68 processes the eighth bit of the data. Further, 11 is a CPU that controls the system, 12 is a data bus that serves as a data path, 13 is a bidirectional buffer that passes data input by external control in the right or left direction, and 14 is an address decoder that decodes an address. , 15 is a first AND, 16 is a first-in first-out memory, 17 is a first OR, 18 is a shift register as delay means for setting a certain delay time to an input signal, 19
Is a second AND, 20 is a second OR, 21 is a third OR, 22 is a command reset register, 23 is a second first-in first-out memory, and 24 is a fourth OR. Each of the circuits 13 to 24 corresponds to the command register circuit of the present invention.

Data corresponding to the command shown in FIG. 3 (b), address, write pulse and read pulse shown in FIG. 3 (a) are output from the CPU 11 via the data bus 12, respectively, and further processed by the CPU 11. The interrupt signal shown in FIG. 3E generated by the circuit 6 is input.

The data corresponding to the command 1 shown in FIG. 3B is opened rightward when the read pulse is at the “Low” level, passes through the bidirectional buffer 13 and the terminal D of the first first-in first-out memory 16. Has been entered. At this time CPU11
The address output from is decoded by the address decoder 14 into an address for the command register, and the first AND15
Is added to the first AND 15 and is AND-combined with the write pulses 1 to n which are both input to the first AND 15.
Generates a write pulse for the first first-in first-out memory 16
To the terminal WCK. The rising edge of this write pulse causes the terminal D of the first
, The data corresponding to the commands 1 to n input to the memory 16 are continuously latched, and the data is successively written to the first first-in first-out memory 16 from the next. The write pulse from the CPU 11, the output of the address decoder 14, and the data output from the bidirectional buffer 13 are both command reset registers.
The output of the command reset register 22 is applied to the terminals * R of the first first-in first-out memory 16, the shift register 18, and the second first-in first-out memory 23, and resets them.

A shift register 18 is provided to guarantee a delay time until the first write pulse 1 to the first first-in first-out memory 16 reads out data corresponding to the command 1 in FIG. Has been. That is, the write pulse 1 shown in (a) which is the output of the first AND15.
The input to the terminal D of the shift register 18 the output of the rising edge through the first OR 17, is controlled to clock input together outputs of the first-time readout pulse shifted from the terminal Q _X of the shift register 18 And the second AND19, the second OR
After 20, the signal is added to the terminal RCK of the first first-in first-out memory 16. Therefore, first, the data corresponding to the command 1 written in the first first-in first-out memory 16 is read out and becomes the command 1 shown in FIG.
Is sent to the first processing unit 61 for processing. When the first processing unit 61 finishes processing the data corresponding to the command 1 in (d), the second read pulse 2 and the command 1 shown in FIG. 3 (c) for the next read Both signals of status 1 indicating that the data processing is completed are output from the first processing unit 61, respectively.

The read pulse is divided into two, one of which is applied to the terminal WCK of the second first-in first-out memory 23. Then, the status 1 output from the first processing unit 61 and input to the terminal D via the fourth OR 24 is written in the second first-in first-out memory 23 by the read pulse applied to the terminal WCK. Another other read pulse 2 is the second OR
The read pulse 2 is applied to the terminal RCK of the first first-in first-out memory 16 via 20 and starts reading data corresponding to the next command 2. Then, the data read from the first first-in first-out memory 16 by the read-out pulse 2 is applied to the second processing unit 62 to process the command 2 and further read the data from the first first-in first-out memory 16. Read pulse 3 for status and status 2
And generate

Hereinafter, this operation is repeated repeatedly until the commands 3 to n written in the first first-in first-out memory 16 are output. After outputting the first write pulse, the shift register 18 works to lock the write pulse by the lock signal from the terminal Q _A until the CPU 11 starts the next write.

Note that the CPU 11 outputs an interrupt signal which is output when the command processing of the processing circuit 6 is completed, that is, when the interrupt signal indicates that the interrupt is enabled as shown in FIG.
When recognizing that the signal h 'has been input, a read pulse is output at an arbitrary time and applied to the second first-in first-out memory 23 and the bidirectional buffer 13. Therefore, the statuses written in the second first-in first-out memory 23 from the first processing unit 61 to the eighth processing unit 68 of the processing circuit 6 can be read out at any time and in any order. The read status is obtained by opening the path of the bidirectional buffer 13 to the left and outputting the output read from the second first-in first-out memory 23 to the bidirectional buffer 13.
By transferring from 13 to the CPU 11 via the data bus 12, C
The PU 11 can recognize that the operation of the processing circuit 6 is completed.

〔The invention's effect〕

As apparent from the above description, according to the present invention, the central processing unit can write a command without reading the processing circuit status, so that the central processing unit reduces the time for reading the status and the end confirmation time. become able to.

Therefore, the load on the software of the central processing unit can be reduced and the processing speed can be increased, which greatly contributes to improving the performance of the central processing unit system.

[Brief description of the drawings]

 FIG. 1 is a circuit diagram showing a principle configuration of the present invention, FIG. 2 is a diagram showing a circuit configuration of one embodiment of the present invention, FIG. 3 is a time chart of one embodiment of the present invention, FIG. FIG. 5 is a diagram showing a circuit configuration of a conventional example, and FIG. 5 is a diagram showing a time chart of the conventional example. In the figure, 1 is a central processing unit, 2 is a data bus, 3 is a first-in-first-out memory, 4 is a delay means, 5 is a second-in-first-out memory, and 6 is a processing circuit.

Claims (1)

(57) [Claims] 1. A central processing unit that sends data and a write signal corresponding to a command, and a plurality of first processing units to n-th processing units that operate according to activation from the central processing unit and execute the processing of the command. A delay circuit for delaying the initial signal in the write signal between the processing circuit having the: and the output of the delay circuit and the processing results of the plurality of first processing units to the n-th processing unit. A first first-in first-out memory for outputting a start command to the plurality of first processing units to the n-th processing unit, and a start command from the plurality of first processing units to the n-th processing unit. A second first-in first-out memory for notifying a status to the central processing unit; and providing an order of sequentially operating the plurality of first processing units to the n-th processing unit from the central processing unit. A command register circuit characterized in that the command register circuit is set continuously and can be activated to the next (k + 1) th processing unit without waiting for an end status from a certain kth processing unit.