SU1605247A1 - Multiprocessor system - Google Patents

Abstract

The invention relates to computing and can be used in multiprocessor systems with common interprocessor exchange buses for organizing interrupt processing from various I / O units. The purpose of the invention is to expand the scope by buffering interrupt vectors and reducing the amount of equipment. The system contains 1 ₁ –1 _K interface blocks, 2 ₁ –2 _M connection blocks, 3 ₁ –3 _K processing blocks, 4 ₁ –4 _M input / output blocks, interprocessor exchange bus 5, exchange control block 6. The goal is achieved by accessing the bus and pre-accumulating the transmitted interrupt vectors. 1 hp f-ly, 5 ill.

Description

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The invention relates to computing and can be used in multiprocessor systems with common interprocessor exchange buses for organizing interrupt processing from various I / O units.

The purpose of the invention is to expand the scope and reduce the volume of equipment.

Figure 1 is given a functional diagram of a multiprocessor system; Fig. 2 is a functional block diagram of the connection; Fig. 3 is a functional diagram of the interface block; Fig. 4 is a timing diagram of the operation of the control unit; FIG. 3 is a diagram of the control unit.

The system (Fig. 1) contains blocks 1 (-1 X gateways, connection blocks, processing blocks 34-3k, input / output blocks, 5 m interprocessor exchange bus, exchange control block 6.

The connection unit 2 (FIG. 2) contains a decoder 7, a register 8, a control node 9, a trunk amplifier 10.. V

15 FIFO type memory of the corresponding interface unit 1 and a message, where part of the bits of register 8 is not used for storing the address, another part is for storing the message, and the codes of the specified bits of register 8 are connected respectively to the lines 22 of the address and data bus lines 25 5 interprocessor exchange.

Thus, all I / O blocks 4 are distributed between blocks 3. When a break occurs in one of the I / O blocks 4 or in several of them, the interrupt request signal on line 26 goes to the first input of node 9. This signal initiates the procedure capturing the interprocessor exchange bus, the algorithm of which is determined by the specific implementation of the interprocessor exchange bus of the multiprocessor system, the second inputs / outputs of the node 9 receive the exchange control signals of the interprocessor exchange bus 5. According to these signals, node 9 exposes at the second output 29 a signal that opens amplifier 10 of the interrupt vector and register 8. Thus

The interfacing unit 1 (Fig. 3) contains the DZ, in the event of the occurrence of intercomparison circuits 11 and 12, the first 13 and second 14 inputs of the block number, the node. 15 memory, item 16, register 17 messages, trunk amplifier 18,

The control unit 9 (FIG. 5) comprises an AND element 19, amplifiers 20 and 20, and a trigger 21.

The diagrams also show the address bus 22, the exchange synchronization bus 23, the data transmission bus 24, the information bus 25, the interrupt demand output 26, the interrupt vector output gate 27, the interrupt enable input 28, the sample sign output 29, the interrupt vector output 30, output 31 read controls, interrupt request input 32, information input 33, interrupt enable output 34, address output 35.

A multiprocessor system works as follows.

During system initialization or in the process of solving a task, blocks 3 distribute I / O blocks 4 according to the required criteria of the problem to be solved, each block 3 entering into all logically connected blocks 2 in register 8 a node address

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The SRI of the interface with the I / O unit 4 forms the usual cycle of recording information on the interprocessor exchange bus, in which the contents of register 8 are set on line 22 of the address of the interprocessor exchange bus 5, and the line 25 of the data of the interprocessor exchange 5 is exchanged and a message, if any, in a similar manner. One and blocks 3 may cause an interruption of another block 3 by performing a write operation on the interprocess communication bus 5 at the individual address of the memory node 15. In this case, all the 1 interconnection exchange units 1 connected to the interprocessor exchange buses 5 analyze the address of the exchange cycle, which follows the address line 22 to the inputs of the comparison circuits 11. Depending on the address, a comparison circuit 11 is activated in one of the matching .1 blocks. The signal from the output of the comparison circuit 11 is inputted to the recording resolution of the memory node 15, to the synchronization input of the recording of which a write signal is received that is 24. interrupt5

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The SRI of the interface with the I / O unit 4 forms the usual cycle of recording information on the interprocessor exchange bus, in which the line 22 of the interprocessor exchange bus 5 exposes the contents of register 8, and on the data line 25 of the interprocessor exchange bus 5 the message, if there is one. Similarly, one of the blocks 3 may cause an interruption of any other block 3 by executing the write operation on the interprocessor exchange bus 5 at the individual address of the memory node 15. In this case, all the 1 interfacing exchange units connected to the interprocessor exchange bus 5 analyze the address of the exchange cycle, which arrives at the inputs 22 of the comparison circuits 11. Depending on the address, a comparison circuit 11 is activated in one of the matching .1 blocks. The signal from the output of the comparison circuit 11 is fed to the input of the recording resolution of the memory node 15, to the input of the syncro. the recording of which receives a write signal 24 each. Thus, in one of all the conjugate blocks 1, the operations of recording the interrupt vector and the message to the memory node 15 are performed.

Such a situation is possible, when several blocks 2 and blocks 3 simultaneously perform a write operation in one of the 1 conjugation blocks. These operations follow one after another continuously over the interprocessor exchange bus with a much shorter time interval than the processing time of one breakdown by block 3. To eliminate the conflict (message loss), a FIFO memory type 15, which has a certain depth, is used. access from a specific implementation, and access discipline first entered - first entered. As such a memory, it is possible to use a KR1002IR1 microcircuit, which has a capacity of 32 cells of 8 bits, or execute such a memory on a different element base. Such a memory is capable of accumulating messages and interrupt vectors and increasing them to the processor as it is needed. After recording the information in memory node 15 on line 32, an interrupt request signal is set, which is fed to the corresponding input of block 3. If interrupts are enabled, block 3 sets the interrupt vector read signal on the back line, producing the first recorded from node 15 vector memory on the data line 33, and rewrites the message from the memory node 15 to the message register 17, which is matched by block 3 when processing an alert. Thus, the recorded interrupt vector and message are deleted from the memory node 15.

If there is no more memory in node 15

interrupt and message vectors, the demand signal for an interruption on line 32 is removed, and if so, it remains active as long as the block

3 will not produce as many interrupt cycles as many times the operation of recording the distortion vectors and messages in memory node 15 from blocks 2 or 3 is performed. After each interruption cycle, block 3 performs a message reading operation that goes to the first input of the comparison circuit 12, to the second input of which the address of the register of 17 messages is supplied in the address space of block 3. The signal from the output of the comparison circuit 12 is fed to

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The input of the element is AND 16, the second input of which receives the read signal of block 3 via line 31. From the output of the element AND 16, the signal arrives at the input of the read permission of the register 17 of the message, on which the data line of the register 3 sets up the register register 17 posts.

An example of the implementation of an interprocess communication bus exchange protocol at the time of transmission of the interrupt vector from I / O blocks to block 3 is shown in Fig. 4, Fig. 5 shows an example of implementation of control node 9 for implementing this protocol.

The I / O unit 4 sets an interrupt request signal (TL), which enters via line 26 to input 1 of node 9. With this signal, node 9 generates a request signal line at the inputs-outputs 2 of node 9, which via lines 23 goes to the bus interprocessor exchange. In response to a request for a trunk request, the interprocessor exchange bus arbiter, which is part of a known exchange control unit, sets a signal to allow the capture of the GO trunk, which

0 via line 23 comes from node 9. The latter, in response to the GO signal, generates an interrupt enable signal that goes through line 28 to the corresponding input of block 4. In response to this signal, block 4 sets the interrupt vector strobe signal (SVP) to line 27 and exposes the interrupt vector to the bus 30. On the SVP signal, the node 9 generates a signal for acknowledging the capture of the trunk, which goes via lines 23 to the interprocessor exchange bus and starts the formation of the trunk loop in the trunk controller (also included in

with the exchange control block): when the signal is B-busy, with a delay of 100 NS, the strobe of the dan1x S1 is issued and the receiver waits for a response from the receiver (strobe S2). The B-busy signal enters the inputs / outputs of node 9, where node 9 generates a WD write signal at the inputs / outputs 2, a signal to open the interrupt vector keys, addresses and messages on the interprocessor exchange bus on line 29. After the interrupt vector is written and messages to the memory node 15, the receiving device sets the signal S2 (data received). By this signal the controller

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interprocess communication bus removes the signal S1. Block 9 removes the interrupt enable signal (TL) via line 28, which unit 4 removes the interrupt demand signal (TL) and stall vector strobe (TST) strobe. By removing these signals, node 9 removes RO, RI signals, the interprocessor exchange bus arbiter removes the GO signal, the write cycle, thus ends.

Claims (2)

1. A multiprocessor system containing K processing units, K interface blocks, M I / O blocks, M connection blocks, an exchange control block, characterized in that, with the aim of expanding the field of application by buffering interrupt vectors and reducing equipment , Рth (Р 1, к) interface block contains the first and second comparison circuits, the AND element, the message register, the trunk amplifier, the memory node, and the address input of the Pth processing block is connected to the first input of the first comparison circuit P- second mate the input and output of which are connected respectively to the first input of the number of the P-th interface block and to the first input of the element I, the second input and output of which are connected respectively to the control output of the reading of the P-th processing unit and to the control input of reading the register of messages whose output is combined through the INSTALLATION OR with the output of the trunk amplifier and connected to the information input of the P-th processing unit, the output of resolution of which is connected to the control input of the trunk amplifier, with the input of the recording control A message source and with the memory control input of the memory node, the output of which is connected to the information inputs of the message register and the main amplifier, the ready output and the memory input of the memory node are connected respectively to the input of the demand of the P-processing unit and the second circuit output comparing this, the first input of which is connected to the second input of the number of the interface unit, and the Bth (in 1, M) connection block with 0 five 0 five 0 five 0 five 0 five holds the decoder, register, control node, trunk amplifier, whose information input is connected to the output of the interrupt vector B of the I / O block, the output of the vector strobe is connected to the initialization input of the control node, and the output of the resolution of the short circuit is connected to the same input In the i-th I / O unit, the output of the termination requirement of which is connected to the input of the condition of the control node, the output of the sample feature of which is connected to the control input of the main amplifier and to the control input of the register, the write enable input of which is connected to the output of the decoder, the output of the exchange request of the P th processing block is connected to the P input of the request of the exchange control block, the output of the exchange request of the control node of the b th connection block is connected to (K + B) - The request input of the exchange control unit, the request exchange acknowledgment input of the Pth processing block is connected to the Рth output confirmation input of the exchange control control unit, the (P + B) output request confirmation of which is connected to the input confirmation acknowledgment of the exchange request control block В-г About the connection block, the address outputs of all processing blocks are combined and connected to the address inputs of all I / O blocks, with information inputs of the decoders of all connection blocks with the second information inputs of the second comparison circuits of all interfaces, and with the first outputs of registers of all connection blocks, information the inputs-outputs of all processing units are combined and connected to informational inputs-outputs of all input-output units, with informational inputs and second outputs of registers, with outputs a mag of the ramp amplifiers of all connection blocks with information inputs of the memory nodes of all interface blocks, the output of the sign of the exchange control recording is connected to the inputs of the record management of the memory nodes of all the interface blocks and registers of all the connection blocks, the synchronization inputs-outputs of the exchange control block are connected to the inputs - sync output outputs of the control unit of all connection blocks. 2. Pop-up system 1, characterized in that the control unit of the connecting block of the connection unit contains an element, two amplifiers and a trigger, wherein the request confirmation input is connected to the first input of the element And and to the trigger input, the output of which is connected to the interrupt enable output of the control node , the input of which is connected to the second input of the AND element, the output of which is connected to the first synchronization output of the exchange, the control node No, the outputs of the first and second amplifiers are connected respectively to the output of the exchange request and the second synchronization output of the control node, the initialization input and the second synchronization input of which are connected respectively to the input of the first amplifier and the trigger installation input. connected to the input of the second amplifier and to the output of the characteristic of the sample of the control unit. Fiz. Fi9.5 Editor N Dumb Compiled by A.Afanasyev Tehred L.Setadyukova Proofreader S.Yevkun Order 3454 Circulation 575 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology 113035, Moscow, Zh-35, Raushsk nab 4/5 Subscription