SU1325479A1 - Device for priority access to common memory - Google Patents

Abstract

The invention relates to computing, in particular, to means providing asynchronous access of computers to shared memory. The purpose of the invention is to increase speed. The control device contains potential input memory triggers 1 and 2, sequence block 3, elements AND 4-9, elements NOT 10 and 11, inputs 12 and 13 Request, the device response input 14 and outputs 15-20. The device, when requested on one of the channels, blocks access on the other channel until the end of the exchange. 2 Il. 1U 15 O) with 77 S 8 79 7/1 20 78 76 Figure 1

Description

The invention relates to computing technology and can be used in computing systems for organizing the operation of two digital computers on a common memory field.

The purpose of the invention is to improve the speed and reliability of the device.

Figure 1 shows the functional15

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nal device diagram; in Fig. 2, the signal to the first canap comes a signal to the national sequence block diagram.

The device contains triggers 1 and 2, sequence block 3, elements AND 4-9, elements NOT 10 and 11, inputs 12 and 13 of the request, input 14 of the response from the general memory, outputs 15 and 16 of accessing the General memory, outputs 17 and 18, the directional selection, the outputs 19 and 20 of the response of the device. Block 3 contains. Elements 21 and 22.

Ouch; the three works as follows.

In the initial state, the low-level potentials O are created at the inputs 12-14 of the interfaced equipment, and low-level potentials are also formed at its outputs 15-20, since low potentials are created at the outputs of elements 4 and 5, which leads to the formation of at the outputs of the block 3 high level signals .1 and O at the output of the elements NOT 10 and 11. At the same time, the inputs 1 and 2 of the gates of the flip-flops 1 and 2 support the signals 1, and the O outputs are recorded at the single outputs.

At the moment of passing through one of the inputs 12 and 13 of the request for signal 1 (let it be the request signal for input 12), the Request 1 signal is written to the trigger 1, and a high level 1 potential is formed at its single output. In connection with the presence of both inputs element 4 of signal 1, signal 1 is also formed at its output and 0 is recorded in the single arm of the trigger, while trigger 2 is locked at the gate input, signals 1 and O are formed at outputs 15, 17 and 16, 18, respectively.

At output 17, the device allows access to the shared memory via the first channel, and at output 15 a high level potential is formed, on the leading edge of which the general memory exchanges information when ready, at the end of which a signal 1 is generated at input 14 computational

The request on input 13 of the device, t ger 2 does not record the incoming signal of the end of the exchange from the first computer, but immediately after the end of the exchange, when the unit 3 output is again (1 is formed, the Request signal is recorded in block 3 and is inactive exchange of the formation of the second computational machine. I

With the simultaneous arrival of both computers, the Request to Inputs 12 and 13, the order of processing the requests is arbitrary and is determined by the deviations of the parameters of Block 3, first exchanging information with the RPF of one machine and then immediately after the other.

Claims (1)

Formula invented A priority access device to a shared memory containing two circuits, two AND elements, the information input of the first trigger is the first input of the device request and is connected to the first input of the first I element, the second input of which is connected to the forward output of the first trigger information the input of the second trigger is the BTopbiM input of the device request and is connected to the first input of the second element AND, the second input to 45 of the second one is connected to a direct exit to a horny trigger, which differs from the fact that, in order to increase the relationship, it additionally contains four elements And, two elements 50 NOT and a queue block, with the output of the first and second elements being AND connected to the first and second inputs of the queue, respectively; the first BTopoi outputs of the queue with 55 dinene with the gates of the first and second triggers, respectively, the inputs of the first and second elements are NOT connected to the first and second outputs of the sequence block 35 40 machine to remove the signal at the input 12 of the request. After that, the device circuit is reset. In the case of a signal arrival. A request on input 13 on the outputs 16, 18 and 20 signals 1 are generated. If during the exchange of information, suppose five 0 five 0  the first canap signal comes The request on the device input 13, the trigger 2 does not record the incoming signal of the end of the exchange from the first computer, but immediately after the end of the exchange, when the unit 3 output is again (1 is formed, the request signal is recorded in block 3 and the information is not communicated second computer. I When signals from both computers arrive at the same time. The request is on inputs 12 and 13, the order of requests processing by the device is arbitrary and is determined by the deviations of the parameters of block 3, first exchanging information with the RPF of one machine, and after the end immediately with the other. Invention Formula A shared memory priority access device containing two triggers, two AND elements, the information input of the first trigger is the first input of the device request and connected to the first input of the first AND element, the second input of which is connected to the forward output of the first trigger, information input of the second trigger is the BTopbiM input of the device request and is connected to the first input of the second element AND, the second input of which is connected to the forward output of the second trigger, characterized in that, in order to improve speed, Four elements are additionally introduced, two elements 0 NOT and a queue block, with the outputs of the first and second elements I connected to the first and second inputs of the sequence block, respectively, the first and BTopoi outputs of the sequence block are connected to the gates of the first and second triggers, respectively, the inputs of the first and second elements are NOT connected to the first and the second output of the priority block corresponds to 5 0 but, the output of the first element is NOT the first output of the device direction selection and is connected to the first inputs of the third and fourth AND elements, the output of the second element is NOT the second output of the device direction selection and is connected to the first inputs of the fifth and sixth elements AND, the first and The second elements And are connected to the second inputs of the sixth Editor V. Petrash Compiled by V. Borodin Tehred L. Serdyukova Order 3111/45 Draw 672 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 and the fourth And elements, respectively, the outputs of the fourth and sixth And elements are the first and second outputs for accessing the shared memory of the device, the outputs of the third and fifth elements for And are the first and second outputs of the device response, the input of the general memory response of the device is connected to the second the inputs of the third and nth elements And, E 229fig, g Proofreader V. But ha