RU1786490C - Device for interfacing microcomputers with communication channels - Google Patents

Abstract

The invention relates to computing. An object of the invention is to expand the number of served-links. The device comprises two address selectors, a channel transceiver, an interrupt vector output unit, a line transceiver unit, two AND elements, a trigger, a group number register and a group number setting unit, as well as an address information, control bus and microcomputer response bus. Thanks to the introduction of the second selector, two AND elements, a trigger, a group number register and a group number setting unit, as well as new communications, the number of connected external devices has been expanded to a value of 256. i.e. a significantly larger number of possible interrupt vectors. 4 ill.

Description

The invention relates to the field of computer engineering and can be used in systems of international telegraph communication, tele-signaling and telecontrol, in automated control systems, etc.

The device is designed to communicate microcomputers with external devices, in particular receivers and transmitters of start-stop telegraph combinations.

An object of the invention is to expand the number of served communication channels.

This goal is achieved in that in a device for interfacing a microcomputer with communication channels containing a first address selector, a channel transceiver, an interrupt vector output unit and a line transceiver unit, the groups of linear inputs and outputs of which are corresponding groups of inputs and outputs of the device for connections to the outputs and inputs of the communication channels, and the group of outputs interrupt request and the group of sample inputs are respectively connected to the group of inputs of the output unit of the interrupt vector and the group of address the outputs of the first address selector, the group of control outputs and the data confirmation input of which are connected respectively to the group of control inputs and the output of the channel transceiver, the first group of information inputs and outputs of which is the group of inputs and outputs of the device for connecting to the address and information bus of the microcomputer and is connected with a group of address outputs of the interrupt vector output unit and a group of information inputs of the first address selector, a group of control inputs and a synchronization output which which are the corresponding group of inputs and the output of the device for connecting to the control bus and the response bus of the microcomputer and are connected respectively to the input synchronization input and the synchronization output of the vector output unit

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interruptions, the second group of information inputs and outputs of the channel transceiver is connected to the group of information inputs and outputs of the linear transceiver unit, a second address selector, two AND elements, a trigger, a group number register and a group number setting unit are introduced, the group of information inputs and a group of control the inputs of the second address selector are connected to the corresponding groups of inputs / outputs and inputs of the device for connecting to the address-information bus and the control bus of the microcomputer, and the output with synchronization -: connected to the output of the device to the microcomputer's response bus and connected to the first input of the first AND element, the second input and output of which are connected respectively to the interrupt enable output of the interrupt vector issuing unit and the trigger setup input, reset input and information input which are connected respectively to the reset input of the device and the bus of the zero potential of the device, and the sync input is connected to the address output of the second address selector and the first input of the second element L, the second input ohm and the output, respectively connected to the output of the trigger and the input of the sample register of the group number, the group of information inputs of which is connected to the group of outputs of the unit for setting the group number, the group of outputs of the group number register and the third input of the first element And are connected respectively to the group of input-output and device connecting to the address information bus and the microcomputer interrupt provision bus. .; . -. ....

Figure 1 shows a diagram of the proposed device; figure 2 is a timing diagram of the proposed device: figure 3 is an example implementation of the proposed device; in Fig.4 is an example of the implementation of the status registers and the generation circuitry of the request for interruption request from Fig.3:

The device contains (Fig. 1.) an address-information, control bus and a response bus of the microcomputer 1 (Fig. 1 Q is a bus, then an external bus), a second address selector 2 (group), a first selector 3, a channel transceiver 4 , interrupt vector output unit 5, internal bus 6, line transceiver block and interrupt request unit 7, first 8 AND element, trigger 9, second 10 AND element, unit 11 for setting the group number of external devices and register 12 for the group number of external devices. The group of linear inputs and outputs of the block 7 of linear transceivers are the corresponding groups of inputs and outputs of the device for connecting to the outputs and inputs of the communication channels, and the group of interrupt request outputs and the group of sample inputs are respectively connected to the group of inputs of the interrupt vector output unit 5 and the group address outputs of the first address selector 3, a group of controllers, outputs and input

confirming the data of which are connected respectively to the group of control inputs and the output of the channel transceiver 4, the first group of information inputs / outputs. of which is the group

. inputs and outputs of the device for connecting to the address-information bus of the microcomputer and is connected to the group of address outputs of the block 5 for outputting the interrupt vector and the group of information inputs of the first address selector 3, group

 control inputs and the synchronization output of which are appropriate

group of inputs and outputs of the device for

connections to control bus and bus

the response of the microcomputer and are connected respectively to the input synchronization input and output synchronization unit 5 of the output of the interrupt vector, the second group of information input-output channel

transceiver. (Fig. 1 internal data bus) is connected to a group of information inputs and outputs 6 of a block 7 of linear transceivers, a group of information inputs and a group of control inputs of the second

the address selector 2 is connected to the corresponding groups of inputs-outputs and inputs of the device for connecting to

 address information bus and control bus 1 of the microcomputer, and the synchronization output is connected to the output of the device for connecting to the response bus of the microcomputer and

 connected to the first we enter the first 8 AND element, the second input and output of which are connected respectively to the interrupt enable output of block 5 of the interrupt vector output and the installation input

trigger 9, the reset input and information input of which are connected respectively to the reset input of the device and the zero potential bus, and the sync input is connected to the address output of the second address selector 2 and the first input of the second 10 AND element, the second input and output connected respectively to the output of trigger 9 and the input of the register selection 12 is the group number, a group of information that is connected to the group of outputs of the block 11 for setting the group number, the group of outputs of the register of the group number and the third input of the first 8 element AND respectively with enes

a group of inputs / outputs and an input of a device for connecting to an address information bus and a microcomputer interrupt provision bus.

Fig. 3 shows an example of the implementation of one of 15 cells of the same type in a microcomputer communication circuit with 120 external devices. All cell elements are identical except for address selector 2, which is common to all cells.

In the first address selector 3 and second address selector 2, the main element is the K588BT1 chip, selector address 2-176200, the range of selector 3 addresses from 175000 to 175736 (for all 15 cells), a signal is generated at the output of the OR element of address selector 3 , selecting a channel transceiver, its logical elements AND generate control signals in block 7. Channel transceiver 4 is implemented on K588BA1. The interrupt vector issuing unit 5 is based on K588BH1 microcircuits: a block 7 of linear transceivers and interrupt requests is also disclosed, in which the linear transceivers are K1002XL1 microcircuits, and the status registers and the interrupt request generation circuit are implemented on elements of the 561st series of the type LN1, TM2, LN2, LE5, LA7; register 12 - chip K561L H1.

Fig. 4 is a circuit diagram of a state register and an interrupt request signal generating circuit.

The composition of the electrical circuit includes: elements NAND 13,14,15 and 16; elements NOT 17 and 18; triggers 19 and 20; bus drivers 21, 22, 23 and 24, each including six gated buffer inverters.

At the heart of the channel transceiver. 4 independent software-accessible elements for writing and reading (bit) implemented on triggers 19 and 20. Logical O and 1 are written to triggers 19 and 20 by a sync input with a signal from AND-NOT 13 elements, the first inputs of which are allowed by signals from the outputs of the address selector 1, and their second inputs receive a pulse WR (write) from K588BT1 block 3 through the elements. NOT 17 and NOT 14..

Information from the triggers 19 and 20 to the internal data bus (connected through the channel transceiver 4 to Oshina) comes through the bus drivers 21 ... 24, if the RD signal (read) through the And 16 and NOT elements is supplied to their inputs 18. allowed by signals from the address selector 1.

When reading information from the status registers of the corresponding receivers and transmitters of block 7. The following bits of the receiver registers 5 are read at the same time: ADO - error in the stop element (M01), AD2 - error of overflow (OG), AD5 - error in checking for clarity (CH ), AD6 - interruption is allowed, AD7 - information is received in the buffer register

0 receiver (RARS); bits of the transmitter status register: AD6 - interrupt enabled, AD7 - buffer register free (RATG). The values of the bits ADO, AD2, AD5, AD7 are formed in transceivers

5 to 100100XL1 of block 7, and the values of HELL 6 are taken from the zero arm of triggers 19 and 20.

In state 1 (interruptions are disabled) - triggers 19 and 20 are set in recording mode when fed to the AD6 line

0 internal bus 6 signal with a level of + 5V (logical O in bus 1), as well as a reset signal or a RESET command.

The generation of the interrupt request signals INTA and INTB is done by AND elements 15.

5 The device operates as follows.

Communication with the computer is carried out via external bus 1. Communication with external devices (receivers and transmitters of information) is carried out at the inputs of PR.M1 ... PRMt and the output of PD1 ... PDt of unit 7, where m is the number of transmitters and receivers, respectively, served by one cell, n is the number of cells (figure 1).

5 Work with external devices begins by setting the interruption request triggers (2pl triggers) in block 7 of line transceivers and interrupt request to the appropriate state. The corresponding interrupt enable trigger is selected by the signal from the output of the first address selector 3 (L lines) and is set to enable or disable in accordance

5 with the value of bit D6 of the data received from the computer via the external bus 1 circuit, the channel transceiver 4, the internal data bus, triggers 19, 20. If information is supplied via the same circuit to block 7

0 to the transmitter data register selected using the first address selector 3, it is immediately transferred to the line (circuit to the PD), and upon completion of transmission, block 7 issues an interrupt request signal via

5 to this information transmitter in the interrupt vector output unit 5 (unless of course the interrupt request enable trigger is set).

Upon receipt of a sequential information sequence (one byte) at the end of reception on the PfP circuit, the block sends an interrupt request signal to block 5 on the corresponding line, which outputs an interrupt request signal (TPR) to external bus 1 and ultimately sets the vector address interrupt A7..AO), with the help of which the information from the computer register 12 determines the address of the data register in block 7 from which, using the first address selector 1. and the channel transceiver 4, it reads the information into an external operational pa-: m Th. ..

A group of external devices with PFP and PD circuits is connected to a structurally complete device (hereinafter referred to as a cell) including all the blocks shown in Fig. 1, except for the second address selector 2, which is a group device. The TPR and SIP signal lines of all cells are connected to the corresponding TPR and SIP lines of the external bus 1. The line of the interrupt confirmation signal 1АК1 from the external bus goes to the zero cell (the first priority of the interrupt processing) leaves this cell as the 1АКО line of the output signal providing interruption and is subsequently connected to the line of the interrupt acknowledgment input signal 1AK1 of the subsequent cell in the order of decreasing priority (increase by 1 cell number). Signal 1AK1 passes through the line of signal 1AKQ in the event that the cell did not exhibit a TPR signal.

If the requirement to interrupt the TPR is set, then the I 8 element is triggered by the signals of the zero level in the lines 1AK1 of the first SMP and the level + 5V in the 1AKG lines and sets the trigger 9 to state T (see the first time sequences in Fig. 2). The CIP signal lines are connected to one of the inputs of the And 8 element in order to exclude; false triggering of trigger 9 due to the delay of the 1AKO signal relative to the 1AK1 signal (see Fig. 2 time interval ti, tz) .. ...:

The signal from the zero arm of trigger 9 allows the group number 12 to pass through the element And 10 of the register selection signal 12, from the output of which, for example, D9 ... D5, binary information corresponding to the cell number (em) is sent to the data lines of bus 1. 8.9 time sequences in FIG. 2) ..

The difference between using the block 5 for outputting interrupt vectors from the known solutions is that it produces 2t vectors once specified and the same for all cells. Suppose, for example, that a cell is structurally designed so that block 7 has 4 receivers

and 4 transmitters (four two-way channels); and the addresses of the interrupt vectors A1, A2 ... A8 are selected equal respectively (the octal code hereinafter) 300, 304, 310, 314, 320, 324, 330, 334. Moreover, after the addresses of the vectors this is also limited. In known solutions, the number of these vectors is the maximum equal to .64 and the same number ,,, is the maximum possible number of serviced external devices,

 With the number of cells equal to 15, the number of external devices served by these cells is 120, including 60 receivers and 60 transmitters. The data coming from the output of register 12 of the external device group number is processed in the following order.

In the first words of the eight interrupt vectors defined by eight. The above addresses set by the block 5 issuing interrupt vectors, the addresses of subroutines A1, A2 ... A8., One of the variants of which can be represented in the form:

A1; MOV R1 @ # PM1; save R1 in. memory cell PM1

MOV @ # 176200, R1; call data from register 12 to R1

ADD # 1750XX, Rii XX for A1 00, for A2-04: for AZ-10. A4-14, A5-20, A6-24; A7-30, A8-34. . :

MOV R1, @ # PM2; transfer of the register address - the state of the external device, which caused an interruption in the memory cell РМ2. . .-. -

MOV @ # PM1, R1; R1 RTI recovery; exit from interrupt 175000 and 175002 - addresses of the state register and data register, respectively, of the first receiver; ...

175004 and 175006 - addresses of the state register and data register, respectively

first transmitter; ,: / -175734 and 175736 — addresses of the registers of the state and: data of the six transmitters; 1 176200 - register address 12 of the group of external devices, decrypted by the second address selector. 2, in the register

Claims (1)

0 12/176200 / in bits D9 ... D5 information is recorded in binary code, equal to the cell number 00000, 00001, 00010, .. 01110 for cells from the 0th to the 14th, inclusive. The formula of the invention neither 5 A device for interfacing microcomputers with communication channels, comprising a first address selector, a channel transceiver, an interrupt vector output unit, and a line transceiver unit, the linear input and output groups of which are corresponding groups of inputs and outputs of the device for connecting to the outputs and communication channel inputs, and the interrupt request output group and the sample input group are respectively connected to the group of inputs of the interrupt vector output unit and the group of address outputs of the first address selector, the group of control outputs and the data confirmation input of which are connected respectively to the group of control inputs and the output of the channel transceiver, the first group of information inputs and outputs of which is the group of inputs and outputs of the device for connecting to the address and information bus of the microcomputer and is connected to the group of address the outputs of the interrupt vector output unit and the group of information inputs of the first address selector, the group of control inputs and the synchronization output of which are respectively a group the strokes and the output of the device for connecting to the control bus and the response bus of the microcomputer and are connected respectively to the input synchronization input and the output of the synchronization output unit of the interrupt vector, the second group of information inputs and outputs of the channel transceiver is connected to the group of information inputs and outputs of the linear transceiver block - sensors, it is noteworthy that, in order to expand the number of serviced communication channels, a second address selector, two And elements, a trigger, a group number register and a block are entered into it to set the group number, moreover, the group of information inputs and the group of control inputs of the second address selector are connected to the corresponding groups of input-outputs and inputs of the device for connecting to the address-information bus and the control bus of the microcomputer, and the synchronization output is connected to the output of the device for connecting to the response line of the microcomputer and is connected to the first input of the first AND element, the second input and output of which are connected respectively to the interrupt enable output of the interrupt vector issuing unit and the setting the trigger input, the reset input and information input of which is connected respectively to the device reset input and the device zero potential bus, and the sync input is connected to the address output of the second address selector and the first input of the second AND element, the second input and output connected respectively to the trigger output and sample input the group number register, the group of information inputs of which is connected to the group of outputs of the group number setting unit, the group of outputs of the group number register and the third input of the first AND element oedineny vhodov- respectively with a group of outputs and an input device for connection to the address-data bus and interrupt bus grant microcomputer. FIG. /. Fig 2 I WҐ