SU1401469A1 - Device for interfacing a computer with controlled objects - Google Patents

Abstract

The invention relates to computing and can be applied to group control of manipulators and assembly equipment in real-time systems. The aim of the invention is to reduce hardware costs. The device contains a communication unit with a computer channel, a register, a decoder, a multiplexer, a counter, a parity control unit, a shift register, a blocking node, a signal analyzer, a transducer signal generator, a buffer memory register, an input / output unit, an interrupt vector register, a unit synchronization, two elements I. 3 z.p. f-ly, 9 ill.

Description

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The invention relates to computing and can be applied to group control of manipulators and assembly and assembly equipment in real-time systems.

The purpose of the invention is to reduce hardware costs.

Figure 1 presents the block diagram of the device; figure 2 - diagram of the signal analyzer; FIG. 3 shows a communication unit with a computer channel; 4 is a diagram of the interrupt signal generator in FIG. 3 is a block node diagram; figure 6 - block diagram of the control of parity; Fig. 7 is a schematic of an interrupt vector register; on Fig - block I / o; figure 9 - block synchronization.

The device for interfacing a computer with control objects (Fig. 1) contains the first communication unit 1 with a computer channel, channel 2 of the computer, group 3 information inputs-outputs of unit 1, information input 4 of the device, register 5, decoder 6, multiplex - ° Sor 7, counter 8, group 9 of information outputs of multiplexer 7, element 10, information input 11 of the device, block 12 parity control, shift register 13, synchronization bus 14, signal analyzer 15, blocking node 16, element 17, interrupt signal generator 18, interrupt supply circuit 19, circuit 20 interrupt request, buffer register 21, memory register 22 of interrupt vector, input / output unit 23, synchronization unit 24.

The signal analyzer 15 (FIG. 2) contains a multiplexer 25, an EXCLUSIVE element OR 26, an AND element 27, and a memory node 28.

The communication unit 1 with the computer channel 2 (FIG. 3) contains a bus driver 29, a decoder 30, an AND 31 element, a trigger 32, And 33 and 34 elements, and an OR 35 element.

Interrupt signal generator 18 (Fig. 4) contains triggers 36 and 37, elements 38 and 39.

The blocking block 16 (FIG. 5) contains an element 40, a trigger 41 and a single-axis 42.

The parity check block 12 (FIG. 6) contains an AND 43 element, trig

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ger 44, trigger 45, elements And 46 and 47.

The interrupt vector register 22 (Fig. 7) contains a jumper dial pad 48 and a bus driver 49.

The input / output unit 23 (FIG. 8) contains a shift register 50, a parity check node 51, a discrete information input input 52, a HE element 53, a shift register 54, an OR element 55, a delay element 56, memory nodes 57 and 58, register 59, modulo two modulator 60, discrete information transfer line 61 to the controlled object.

The synchronization unit 24 (Fig. 9) contains a node 62. The communication with channel 2 of the computer, identical to unit 1, in the group of information outputs uses only one of the bits, for example, the younger one, connected to the D input of trigger 63, and in the group of information inputs the same bit is also used, connected to the output of trigger 64, element AND 65, element OR 66, element 67, one-shot 68, pulse generator 69, counter 70, amplifier register 71 for transmitting clock signals to controlled objects, counter 72 , one-shot 73 and 74.

The device works as follows.

When the power supply B is turned on, the general reset circuit (not shown) of channel 2 generates a signal that sets the initial (zero) state of the triggers 36 and 37 in the interrupt signal generator 18, the triggers 44 and 45 in the control blocks 12 and 51 the parity, the trigger 63 and 64, and the counters 70 and 72 in the synchronization block 24, and the trigger 41 in the blocking block 16 is set to one. As a result, the interrupt signal generator 18 is set to a passive state, the interrupt request signal is not formed on line 20, the Log.1 signal is set to the first input of element 39, and the interrupt grant signal from channel 2 can be transmitted for servicing line 1 9. other devices that have lower priority relative to the proposed device.

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The synchronization unit 24 is also in the passive state, since the signal Log.O from the output of the trigger 64 through the AND 67 element prohibits the operation of the generator 69.

The exchange of information between the device and the computer is carried out through block 1. The computer information exchange cycle is broken. two parts: address and information. In the address part of the machine cycle, information from channel 2 of the computer is passed by bus driver 29 from channel B to channel C and installed at the inputs of register 5 and decoder 30. The higher bits of the code defining the address of addressing the device are connected to the inputs of decoder 30. The lower bits of the code that determine the subaddress for accessing the device registers or the cells of the 28, 57 and 58 memory are connected to the inputs of register 5, and the most significant one (bit Q4 of register 5) defines access through the decoder 6 to one of the specific items. The number of subaddresses is determined by the number of groups of signals analyzed. The address part is separated from the information signal at the first synchronization of block 1. If the address of the address corresponds to the configuration of the decoder 30, then the output of element 31 is set to a logical 1 signal, and the signal on the first synchronous input of block 1 captures the signal of logical 1 at the trigger output 32 and the subaddress code at the outputs of register 5, as well as passage through element 10, switches multiplexer 7 to transmit the subaddress code from the register 5 output to bus 9. If the access code does not match the device, the output of the counter is connected to the bus 9 eight.

In the information part of the cycle, the output from channel 2 passes through the shaper 29 through the group of information outputs of block 1 to the information inputs of nodes 28 and 58 of the RAM. The signal at the second synchronization input of unit 1, having passed through element 34, to the second synchronization input of the decoder 6, will cause, depending on the signal level at the D-input of the decoder 6, the appearance of the signal at the fourth or the first output of the decoder and thereby record information in selected469

Node cell selectable memory node. However, the signal from the output of the element H 34 will pass through the element OR 35 to channel 2, informing the computer about the reception of information by the device.

In the information part of the cycle - Input signal from the third sync-input

Q block 1, having passed through the element AND 33, will switch the bus driver 29 to transfer information from channel A to channel B and, passing to the first gateway of the decoder 5 of the torus 6, will cause, depending on the signal level at the D-input of the decoder 6, the appearance of a signal at the third or second output of the decoder 6, activating the outputs of register 21 or register 59, respectively. In this case, either the information containing c in register 21, or the information of the selected cell of the memory node 57 will be displayed in channel 2 of the computer. At the same time, the signal

5 from the output of the element AND 33 will pass through the element OR 35 to channel 2, informing the computer about the issuance of information from the device.

To finish preparing the device for operation after powering the computer power, it sequentially records the zero code in all cells of the main memory nodes 28 and 58 to prevent sending false commands to the controlled object through the register 54 and false interrupts from the analyzer 15 when the block 24 is turned on sync.

Inclusion of sync block 24

Q is carried out by writing logical 1 to trigger 63 (processing of the computer to the synchronization unit 24 via the node 62, identically described for block 1).

The signal of logic 1 from the output of the trigger 63, arriving at the D input of the trigger 64 and passing through the OR 66 element to its synchronous input, translates it into a single state. Since the first input element And 67 us0U tr 4 ti

set the logical signal 1 s

the output of the one-shot 74, the signal Log.1 from the output of the trigger 64 is transmitted through the element And 67 and excites the one-shot 68, which generates a signal on the second clock line of the sync bus 14. The signal Log.G from the output of the element And 67 also includes a generator 69, as a result

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Those at the outputs of the register of amplifiers 71 on the third line of the sync bus 1D sync signal generate signals controlling the shift of information in the shift registers 13, 50 and 54 and in the interconnected registers of the control object (not shown).

Counters 70 and 72 divide the frequency of the generator pulses 69 with a division factor specifying the number of bits in the transmitted message. The messages exchanged by the device with the controlled object consist of groups, the number of which is determined by the division factor of the counter 72, and the number of bits in the group is the division factor of the counter 70. The number of bits in the group transmitted (received), the message corresponds to the number of bits in the group of analyzed signals.

At the end of the transfer to each group of signals from the output of counter 70, the one-shot 73 is energized and sends a pulse signal to the first sync line of the bus 14 sec. Synchronization. At the end of the message transfer, the one-shot 74 is energized and, through element 67, blocks generator 69, creating a pause between message transfers. At the end of the pulse of the one-shot 74, the blocking of the generator 69 is removed through the AND 67 element, and the one-shot 68 is re-energized.

The synchronization unit 24 is turned off by writing logical O and to the trigger 63. At the same time, if the synchronization unit 24 is in the Pause state, then the first input of the AND 65 element is set to logical level 1, and the signal from the inverse output of the trigger 63 through AND 65 elements and OR 66 passes to the synchronous input of the trigger 64, switches it to the passive state, and through the element 67 it confirms the blocking signal of the generator 69. If at the moment of recording the logical O to the trigger 63 the synchronization unit 24 is in the forwarding state of the message, on D- the entrance trigger 64 sets the logic level O, on the second input of the element AND 65 the level of logical 1 and after the message is sent, the signal from the output of the one-shot 74 passes through the elements 65

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and NII 66, transferring trigger 64 to a passive state.

Thus, it ensures the correct completion of the transfer of the message H1-III to the controlled objects. The state of the computer synchronization unit evaluates in the Input cycle through node 62, the signal from the output of the trigger 64 is read.

The absence of failures in the information received from inputs 11 and 52 is checked by parity blocks 12 and 51 as follows. Each bit of the serial code arriving at the first input of the AND 43 element is built up by pulses of the third sync signal line of the sync bus 14, as a result of which only the gates of the information bits with levels are passed to the gate input of the trigger 44 included in the single-ended divider circuit. logical 1.

The end of the reception of each group of signals is accompanied by a pulse on the first clock line of the synchronization zone 14 connected to the first input of element 47. If at the moment of arrival of this pulse a flashing trigger 44 passes an even number of gates, the trigger 44 is in the initial state, allowing the pulse to exit from the output element And 47 through element And 46 at the output of block 12. The same pulse from the output of element And 47, arriving at the synchronous input of the trigger 45, confirms its initial state. If by the moment of arrival of the pulse, an odd number of gates passes through the first line and the sync signal of the sync bus 14 to the trigger 44, then the signal .1 is set to D-BXO-de flip-flop 45, and the signal Log.O. The pulse from the output of the element AND 47 will switch the trigger 45 to one state, after which the passage of successive pulses through the element AND 47, and consequently, through the element And 46, is blocked. The block returns to its initial state before the next sending of pulses from the second sync line of the sync bus 14 arriving at the reset inputs of the flip-flops 44 and 45.

The information is transferred to the I / O unit 23 as follows. Before the start of each transfer of the leading edge of the signal in the second line of the bus 14 synchronization

ostapav.11ivae-1h; The counter 8 is in the zero state, as a result of which the zero address code is set at the outputs 9, which prepares the work with the zero cells of the nodes 57 and 58 of the memory. The falling edge of this pulse, through the LNI element 55 and the delay element 56, records the contents of the memory zero cell 58 into the register 54.

The transfer is carried out by pulses arriving at the third sync signal line of the sync bus 14,

formed in t-1mat (.1ре 60 mod. two each. Then the computer stops entering information from the memory node 57 of the memory (the input process is described in the description of the operation of block 1). With each input, the sync signal from the second output of the decoder 6 translates register 59 outputs from high impedance clear to active state.

Through the register 50, the device receives information about the parameters of the controlled object and state changes that do not require immediate

at the same time, the leading edge of each imig response, and the computer processed by

pulse is shifted information in the receiving register 50, and the falling edge through the element 53 is the shift in the transmitting register 54. Thus, with a similar organization of the receive and transmit registers in the controlled object, the information is transmitted correctly (first the previously prepared bit is received, and then the transmitter exposes a new bit-information. The completion of the transfer of each group, as indicated in the description of the operation of the synchronization unit 24, is accompanied by a single pulse on the first line of the sync Signals of sync 14.

The leading edge of this pulse is the transfer of information from the register 50 to the cell of the memory node 57, whose address is determined by the state of the counter 8. The trailing edge increases the content of the counter 8 by one, preparing the memory nodes 57 and 58 for work with regular groups of sent signals. The leading edge of this signal, the passage through the first input of the OR 55 element and the delay element 56, records the next group in the register 54.

To analyze information about the state of the controlled object recorded in the memory node 57 and to modify (or confirm) the control information in the computer memory node 58, the synchronization unit 24 periodically turns off the synchronization unit 24 and after receiving information about the transition of the unit 24 to the pause state sending information to the cells of the memory node 58 (the recording process is described in the description of the operation of block 1). The code of each group is supplemented by a parity bit.

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the principle of a periodic survey. Changes in the state of the controlled object that require an immediate response, realizing the operation in real time, are received through the register 13 and are processed by the signal analyzer 15 with the generation of interrupt request signals through the interrupt signal generator 18.

When in the course of operation it becomes necessary to monitor the state of a certain bit in a received message, the computer writes to the node 28 of the operational memory at the address corresponding to the group number containing the controlled bit the setup code of the signal analyzer 15. The tuning code contains the code of the controlled bit number in the group (bits Q1-Q3 of the memory node 28), the allocated bit for setting the expected signal level (bit Q4) and the selected bit with a logic level 1 (bit Q6) to allow the passage signals through the element And 27.

If the control process requires, without waiting for the signal from the selected bit, to disable monitoring of its state, the computer writes a zero code to the operating memory node 28 at the same address, putting the corresponding group of signals into a passive state.

Similarly, independently of each other, the control of other groups of signals received by register 13 in the proposed device or in the same devices connected to channel 2 and synchronization bus 14 and differing from each other in the configuration of jumpers in the decoder 30 and in the dial pad 48.

In the process of receiving by the register 13 of the signal group, the code of the number of this group is set at the output of the counter 8 and, passing through the multiplexer 7 to the address inputs of the operational memory 28, exposes at its outputs the control code of the received signal group. controlled bit from the output of register 13 is transmitted to the output of multiplexer 25. If in the process of sending a group, block 12 does not detect a parity failure, the pulse from the first sync line of the sync bus 14 passes through element 46 on the output of the block 12 and through the element AND 17 enters the third input of the element AND 27. If the level of the controlled discharge at the output of the multiplexer 25 does not match the expected level, the output Q4 of the memory node 28, the output of the EXCLUSIVE OR 26 element sets the logical level Oh, and the pulse through the element And 27 to the output of the signal analyzer 15 does not pass.

With the falling edge from the first sync line of the sync bus 14, the contents of counter 8 are incremented by one, and the device is the first input of the AND 39 element. It is ready to receive and analyze the next group of signals.

If, at the time of monitoring the next group of signals, the level of the controlled bit at the output of multiplexer 25 coincides with the expected level at the output Q4 of the EXCLUSIVE OR 26 element, the pulse from the output of the AND 17 element passes through the AND 27 element to the output of the signal analyzer 15 and switches to one state trigger 36 in the driver 18 interrupt signal.

The output signal from flip-flop 36 prepares the flip-flop 37 for switching and exposes the interrupt demand signal via line 20 to channel 2. At the same time, this signal arrives at the synchronous input of the buffer register 21 and fixes in it the code of the number of the group that caused the interruption. The same signal, arriving at the blocking block 16, will set the logic level O at the output of the element 40 and switch 40

The interrupt supply signal causes the appearance of a signal at the output of the element 38. This signal sets the trigger 36 to the zero state, as a result of which the trigger 37 is prepared for the zero state and the signal from the interrupt signal 20 is removed. from the output of the element g 38 translates the outputs of the bus driver 49 from the state of high impedance to active, and also, having passed through the element e 35, enters channel 2, informing the computer about issuing a code from the device to channel B. As a result in can It will receive the interrupt vector code set by the jumpers of dial pad 48 and will be used by a computer to implement the interrupt service software.

Thereafter, a signal is removed from line 19 of the distributor, which leads to the removal of the signal from the output of the AND 38 element and the translation of the output

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cheat into the zero state trigger 41, as a result of the output of the one-shot 42, an impulse is formed that will overwrite O from the output of the AND 40 element to the sixth bit of the memory node 28 at the address corresponding to the group number that caused the interrupt. This group is in a passive state. In addition, the signal from the output of the trigger 41 will prohibit the passage of pulses from the output: the parity control unit 12 through the H 17 element, thereby ensuring

correct completion,. computer interrupt handling.

The trigger switch 37 occurs when the interrupt signal is received by the synchronizer input of the driver 18.

on the line of the third synchronous input of the unit 1 of the next synchronizing pulse of channel 2, after which the interrupt signal generator 18 enters a state of waiting for the interruption grant signal on line 19, which the computer must respond to in response to the signal on line 20 of the interrupt request. If the signal passing through line 19 is not blocked by devices that have a higher priority, then further signal passing through interrupt supply line 19 through AND 39 is blocked by the signal Log.

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The interrupt grant signal causes the output signal of the element 38 to appear. This signal sets the trigger 36 to the zero state, as a result of which the trigger 37 prepares for the zero state and removes the signal from the interrupt demand line 20. In addition, the signal from the output of the element g 38 translates the outputs of the bus driver 49 from the high impedance state to active, and also, having passed through the element 35, enters channel 2, informing the computer about issuing a code from the device to channel B. As a result, the interrupt code vector set by the jumpers of dial pad 48 will arrive in the channel and is used by the computer for software implementation of the interrupt service.

Thereafter, a signal is removed from line 19 of the distributor, which leads to the removal of the signal from the output of the AND 38 element and the translation of the outputs

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In the form of a high impedance. When the third synchronizing input of the block 1 of the next synchronizing pulse arrives, the trigger 37 is set to the zero state, and the interrupt signal generator 18 returns to the initial state.

To access the desired subroutine, the computer makes additional access to register 21. The signal formed on the third output of the decoder 6 activates the outputs of register 21, and also sets the trigger 41 in the blocking unit 16 to one state. At the first input of the element 17, a signal is established allowing the signals through the element 17 to pass from the output of the parity control unit 12 to the resolution input of the signal analyzer 15.

Claims (4)

1. A device for interfacing a computer with control objects, comprising a communication unit with a computer channel, a register, a decoder, a buffer memory register, a parity check unit, a shift register, a signal analyzer, an interrupt signal generator, and a group of information input-output blocks communication with the computer channel forms a group of input-output devices for connecting to a group of information and address inputs-outputs of a computer, the first synchronized input of the communication unit with a computer channel is connected to the synchronous input of the register and is the input of the device for the first synchronization output of the computer, the second synchronization input of the communication unit with the computer channels is the input of the device for connection to the second synchronization output of the computer, the third synchronization output of the communication unit with the computer channel is connected to the synchronization signal of the interrupt signal generator and is the input of the device for connection to the third the synchronous output of the computer, the first synchronized output of the communication unit with the computer channel is the output of the device for connection to the synchronous input of the computer, the output of the interrupt signal generator demand is the output of the device for so me to the entrance requirements interrupt the computer, the output providing pre20 146912, the interrupt signal generator trigger is the output of the device for connecting to the computer supply interrupt input, the interrupt signal generator allowing output is the device input for connecting the computer interruption supply output, information input The 1Q shift register is connected to the information input of the parity check block and is the device input for connecting to the first information output of the object, up. 15, the information input of the air remover is connected to the information output of the register, a group of information inputs of which is connected to the first group of information outputs of a communication unit with a computer channel, the second group of information outputs of which is connected to the first group of information inputs of a signal analyzer, the second group of information inputs which is connected to the group of information outputs of the shift register, the output of the signal analyzer is connected to the trigger input of the interrupt signal generator, It is distinguished by the fact that, in order to reduce hardware costs, it contains a blocking node, a multiplexer, an input / output unit, an interrupt vector register, a counter, a synchronization unit, two AND elements, and the information input and output of the input / output unit are respectively input and device output for connection Q to the second information output and to the information input of control objects, wherein the group of information outputs of the interrupt vector register and the group of mode inputs and outputs of the synchronization unit state are connected to the group of information inputs / outputs of the communication unit with a computer channel, the first, second, third synchronous input and the clock output of the synchronization unit are, respectively, the inputs and outputs of the device for connecting to the first, second, third synchronization outputs and the first synchronization input of the computer, the second and third synchronization outputs of the unit communications with the computer channel are connected respectively to the first and second gate inputs of the decoder, the first and second outputs of which are connected to grade 35 45 0 five Respectively with the write and read inputs of the I / O unit, the group of information outputs of which is connected to a group of information outputs of the buffer memory register and the group of information inputs of the communication unit with a computer channel, the start input of which is connected to the input of the reading of the interrupt vector register and starting the interrupt signal generator, the interrupt request output of which is connected to the enable input of the blocking node and to the write input of the buffer register of the memory, the read input of which is connected to the setup input the blocking node and the third output of the decoder, the fourth output of which is connected to the clock output of the blocking node and the recording input of the signal analyzer, whose information input is connected to the information output of the blocking node, whose information input is connected to the senior bit of the second group of information outputs of the communication unit with a computer channel, the fourth synchronization exit of which is connected to the first input of the first element I, the second input of which is connected to the synchronous input of the register, the information output group of which is soy inena first group inormatsionnyh multiplexer inputs, the group of information outputs connected to Koto group informatsinnyh input buffer register pa ti, with the group address inputs anaizatora signals and the group address inputs of the input-output unit, a group of information inputs of which connected to the second group of information outputs of the communication unit with a computer channel; the output of the first element I is connected to the control input of the multiplexer, the second group of information: inputs of which are connected to the group of outputs of the counter, 1st counter, input of which is connected to the first synchronous inputs of the parity check unit and the input-output unit and the first synchronized output of the synchronization unit, the second synchronous input of which is connected to the synchronous input of the input-output unit, with the installation input of the counter and with the installation input of the control unit to even st, the second clock input of which is connected to the clock input of the shift register, with three five 0 five 0 five 0 five 0 five This synchronous input I / O and the third synchronized output of synchronization, the enable input of the signal analyzer is connected to the output of the second element I, the first and second inputs of which are connected respectively to the allowing output of the blocking node and to the parity control unit. 2. The device according to claim 1, such that the blocking node contains an element AND, a trigger, a single-oscillator, and the inverse input of the element AND is connected to the synchronous input of the trigger and is the enable input the node, the direct input of the AND element and the single input of the trigger are respectively the information and installation inputs of the node, the output of the trigger is connected to the single-vibrator start input and is the output of the node, the outputs of the AND element and the single-vibrator are respectively information and clock outputs of the node, while The trigger input is connected to the zero potential bus of the device. 3. The device according to claim 1, which means that the input / output unit contains two memory nodes, two shift registers, a register, a modulo two, a parity check node, an OR element, an NOT element, the delay element, the group of information inputs of the first memory node is connected to the group of information inputs of the modulo two adder and forms the group of information inputs of the block; the group of address inputs of the first memory node is connected to I, the group of address inputs of the second memory node and forms the group of address inputs of the block, the write input of the first memory node and the synchronized input of the register are respectively the write and read inputs of the block, the information input of the first shift register is connected to the information input of the parity node and information input node, the output of the second. the shift register and the register output group are respectively the information output and the group of information outputs of the block, the first synchronization input of the parity check node is connected to the first input of the OR element and is the first synchronous input of the block, the installation input of the parity check node is connected to the second input of the OR element and is the second synchronized input of the block, the second synchronized input of the parity check node is connected to the input of the element NO, with the synchronous input of the first shift register and is the third synchronized input of the block, In the I / O unit, the output of the modulo two adder is connected to the information input of the first memory node, the group of information outputs of which is connected to the group of information inputs of the second shift register, the first and second synchronous inputs of which are connected respectively to the outputs of the element HE and the delay element input element the delays are connected to the output of the OR element, the group of outputs of the first shift register and the output of the parity check node are connected respectively to the group of information inputs and the record input and the second memory node, group of information outputs of which is connected to a group of information inputs of register. five ten (446916 4. The device according to claim 1, which means that the parity check block contains two triggers and three AND elements, while the first and second inputs of the first element AND and the first Bbtfi input of the second element AND are respectively the information input, the second and nepBbjM synchronous inputs of the block, the zero input of the first trigger is connected to the zero input of the second trigger, and is the installation input of the block, the output of the third element I is the output of the block, while in the parity control unit the zero output of the second trigger is connected to the second input of the second An element whose output is connected to the first input of the third element I and to the synchronous input of the second trigger, whose information input is connected to the single output of the first trigger, zero output of which is connected to the second input of the third element And, to the information input of the first trigger, synchronous input which is connected with the release of the first element I. 15 20 25 (pui.i Shino O 4d7 FIG. 5 years tsl / g. 6 U / UW..O figl -A -V Ib s 58 Shino „ It 23 67 59 i) and I. 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