SU1160426A1 - Interface for linking computer with peripheral input-output channels - Google Patents

Abstract

DEVICE FOR COUPLING computer to route IO peripherals, containing decoder unit interrupt, the multiplexer, the first and second gain blocks whose inputs-vkody kotorps are respectively first and second input-output device, wherein the first input and output prertany unit connected respectively with the first output and the input of the first gain unit, the second input and output of which are connected respectively to the first and second inputs of the decoder, and the third input to the output of the multiplexer, the first control m input connected to the second output of the decoder, and the first information input to the first output of the second gain unit and the second input of the interrupt unit, characterized in that, in order to reduce hardware costs, the address register and the address selector are entered, the third output of the first gain unit connected to information 0l by address selector addresses and address register, the first input of the second gain block and the third input of the interrupt block, the second and third outputs of which are connected respectively to the second information Mu and the second control inputs of the multiplexer, the control inputs and the output of the selector (L addresses are connected respectively to the fourth output of the first gain unit and the second input of the decoder, the third input and output of which are connected respectively to the third output and fourth input of the interrupt unit, and the fourth input and output - respectively to the second output and the input of the second unit, force 4; The third output and the input of the multiplexer connected to the third and fourth information inputs O) and the output of the address register whose control input is connected to the fifth output of the decoder.

Description

The invention relates to computing and can be used in an automated control system (ACS) and information collection systems with an increased number of peripheral subsystems connected to the address space of the common computer bus used for connecting external devices.

It is known a dp interface of a peripheral system with a computer containing a decoder, a control register; laziness, an interrupt execution unit, an exchange unit, amplification units, which play the role of signal transceivers between the computer and the peripheral system, the first of which is connected to the common bus of the computer, the second - to the trunk of the peripheral system, the outputs of the first gain block are connected respectively to the first inputs of the interrupt execution block, the decoder, the control register of the second gain block, first and second, the inputs of the first amplifier with Connected respectively with the first outputs of the interrupt execution unit and the second gain unit, the second input and output of which are connected to the first input and output of the exchange unit, the second input and output of the exchange unit are connected respectively to the output of the decoder and the second input of the control register flj. The disadvantage of this COCTO device in a limited class of tasks, since it, due to the limited number of addresses of the common computer bus, the space allocated for external devices, allows you to connect to a common computer bus no more than eight such devices to each of which can be connected eight peripheral subsystems containing up to sixteen peripheral devices, each of which can have up to sixteen registers. However, in modern conditions of a constant increase in the flow of information in all branches of the national economy, where computers are already used or will be used by computers, such a number of peripheral subsystems connected to one common computer bus via interface devices cannot satisfy the necessary demand. in collecting, storing, storing and processing information without significant additional costs for new equipment

The closest to the invention in its technical essence is a device for interfacing a computer with a common bus, containing two sets of amplifiers, the inputs-outputs of which are, respectively, the first and second

device inputs, switch and interrupt unit, outputs connected respectively to the first and second inputs of the first gain unit, the third input and the first, second and third outputs are connected respectively to the first outputs and the decoder input, to the first inputs of the data register and control register and block interrupt, the second and third inputs of which are connected respectively to the first and second inputs of the switch, the first output and the input of the second gain block and the output of the control register, the output of the data register is connected to The second input of the second gain unit, the third input and the first output of which are connected respectively to the first output and input of the synchronization unit and the first and second inputs of the exchange control unit whose first output is connected to the third input of the interrupt unit, the second output - to the second control unit input, and the third input - with the output of the decoder and the control inputs of the data and control registers, the switch and the synchronization unit, the second input and output of which are connected respectively to the output and the third input of the control register and T2. A disadvantage of the known device is large hardware costs. The purpose of the invention is to reduce hardware costs. The goal is achieved by the fact that the device containing the decoder, the block of routings, the multiplexer, the first and second blocks of the gain, the inputs-outputs of which are the first and second inputs-outputs of the device, respectively, the first input and output of the interrupt block respectively connected to the first output and the input of the first gain unit, the second input and output of which are connected respectively to the first and second inputs of the decoder, and the third input to the output of the multiplexer, the first control input connected to the second output the decoder's house, and the first information input with the first output of the second gain block and the second input of the interrupt block, entered the address register and the address selector, the third output of the first gain block connected to the information inputs of the address selector and register, the first input of the second gain block and the third input interrupt unit, the second and third outputs of which are connected / respectively to the second information and second control inputs

the multiplexer, the control input and the address selector output are connected respectively to the quarter output of the first Gain unit and the second input of the decoder, the third input and output of which are connected respectively to the third output and fourth input of the interrupt unit, and the fourth input and output respectively to the second output and input the second gain block, the third output and the input of the multiplexer connected to the third and fourth information inputs and the code of the address register whose control input is connected to Besides the output of the decoder.

FIG. 1 shows a block diagram of the proposed device; 2 and 3 are functional diagrams of an interrupt unit and an address selector; in fig. 4-9 - timing charts of the device.

The device contains (Fig. 1) the first gain block 1 containing the trunk transceivers connected through the first 2 outlets of the device to the common computer bus interface, interrupt block 3, multiplexer 4, address register 5, address selector b, decoder 7, the second a gain unit 8 comprising trunk transceivers and connected by buses of a second device output through a trunk 9 to the inputs-outputs of external devices (IU) 10. FIG. 1 shows the internal buses of the device: bus 11, address data, bus 12 of the address of the slave, bus 13 of the data of the slave, bus 14 of the state of the slave, bus 15-17 of the outputs and bus (line) 18-21 of the block 3 interrupt.

bus 22 of the input signal of the device synchronization from a computer, bus 23-25 of the first, second, fourth and fifth inputs of the decoder 7, bus 2629 of the first, second, fourth and fifth outputs of the decoder 7. In addition, in FIG. 1 shows the trunk bus 9 external devices; Bidirectional data bus 30, bus address address bus 31, bus state 32 bus, signal bus 33 Input, signal bus 34 Output, bus 35 input device sync input signal from the bus slave,

Interrupt block 3 contains (Fig. 2) interrupt enable trigger 36, interrupt preparation trigger 37, interrupt request trigger 38, AND elements 39-42, interrupt address encoder 43.

FIG. Figure 2 shows an interrupt grant input signal 44 (RLL) and a signal bus 45 Output, forming the first input of the unit, bus 4 of the output signal providing interruption, and a bus 47 output signal of the interrupt request (TPR), forming the first output of the block.

The address selector 6 contains (FIG. 3) a decoder 48, a register 49, a device selection signal bus 50 and an operation code bus 51 contained in the lower address bits.

The device exchanges data between the computer and external (peripheral) devices 10 in the program exchange mode and in the program interruption mode using standard cycles. Output of the address of the control unit (Fig. 4), Reading the status register (Fig. 5), Outputting data (Fig. 6), Data Output (FIG. 7), Recording the Status Register (FIG. 8), Interrupt Provision (FIG. 9)

In the below considered version of the combined Shared Bus (for example, for electronic computers such as Electronics-60), each cycle contains the address part of the cycle and the information part of the cycle.

The address part of the cycle is initiated by a computer, which assigns the address of the device to the tracks 11 and, on bus 22, a zero level CIA signal, the negative front of which notifies that the address 11 is set to tires 11 (Fig. 4-9). After the address part of the computer cycle, the operation mode is set to in-. of the formational part of the cycle: either the signal Vyshod (on bus 23), specifies the mode of transmitting the data word from the computer (Fig. 4, 6, and 8), or the input signal (on tires 23 and 18), which specifies the mode of data reception in the computer (fig. 5, 7, and 9) In all cases, the positive edge of the PIA signal on bus 11 indicates the end of the cycle. In the program exchange mode, cycles are used. The program interrupt mode is implemented by cycles setting the possibility of computer interruption; those. the sequence of cycles, the output of the address, the recording of the status register and the provision of an interrupt, and then in software mode determines the specific VU 10 that requested the service. The device works as follows. The computer program mode exposes the device address to the busses 11 and the SIA signal to the bus 22. The decoder 48 analyzes the high-order address bits containing the address code of the devices connected to the common bus. If the computer is accessing this device, the decoder 48 generates a signal. The device is selected (HC) at its output, stored in register 49 and broadcast to bus 50. Minor bits of the address, containing the operation code, by a signal on the bus 22 stored in register 49 and transmitted to bus 51. Signals from buses 50 and 51 are sent to decoder 7, which is waiting for a signal Output on bus 23 when implementing the information part of the cycle Record of the address of the control unit (Fig. 4). The computer inserts a data layer on the bus 11, containing the address of the slave 10, with which it exchanges, and the output signal. Having received the signal B of water, the decoder 7 generates on bus 29 a signal that the address of VU address is written to register 5, an acknowledgment signal (VIS) to bus 26. The address of VU from register output 5 through block 8 goes to bus 31. VU 10, identifying its address, set There are 32 signs of its condition on the bus. which, through block 8, arrive at terminal 14. In its state, the device expects from the computer to implement the cycle Read the state register. 266 After the address part of this cycle, the computer exposes an input signal on bus 23, using which the decoder 7 generates a signal on bus 27 for transmission through a multiplexer 4 of state 14 bus 14 to bus 2 and an SIP signal on bus 26 notifying the computer that the state of the specified VU 10 on the tires 2 after reading the state; VU 10 of the computer removes the Input and SIA signals confirming the end of the cycle (Fig. 5). Then the computer implements the data exchange cycle. When data is output from a computer, the last one in the information part of the cycle Data Output (Fig. 6) exposes the data word on bus 11 and the Output signal on bus .23. The decoder 7, using the code on bus 51 and the strobe on bus 50 on the signal. The output on bus 23 generates a signal. The data output on bus 28 via which data from bus 11 is transmitted via block 8 to bus 30 and the signal from bus 28 to bus 34. The signal on bus 34 WU 10 reads the data word from bus 30, signaling the completion of reading the signal SIP WU on bus 35, coming through block 8 to bus 25. On a signal on bus 25, a decoder 7 generates a signal SIP on bus 26, then A computer removing signals Output and SIA on tires 23 and 22 completes the cycle. When entering data into the computer from WU 10, in the information part of the cycle, the input data (Fig. 7) exposes the input signal on bus 23, through which the decoder 7, using signals in register 49 received in the address part of the cycle, generates a signal on bus 27 switching the output of multiplexer 4 with bus 13, and on bus 28 a signal to enter data transmitted via block 8 to bus 33. The signal on bus 33 notifies VU 10, whose address is set on buses 31, of the need to receive data words on buses 30. After issuing the data word to the bus 30, the slave to forms on the bus 35 the gate of the HVAC VU, which enters through the block 8 to the bus 25, causes the formation of the SIP signal on the bus 26. After reading the data word from the slave 10 on the tires 2, the computer ends the cycle tiem signals input and SIA. To work with the initiative, the VU 10 computer configures the device, allowing

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give it an interrupt signal. The computer implements this procedure with the help of a cycle of the state register recording (Fig. 8) as follows. In the address part of the cycle, the computer selects a device and places the corresponding operation code in register 49, and in the information part of the cycle sets a bit of information in the corresponding line 20 of bus 11. Signal output on bus 23, the decoder 7 generates a signal on bus 21 by which the trigger 36 of block 3 (fig. 2) is set to one. At the same time, the decoder 7 drives the CIP signal onto bus 26 to complete the cycle.

If in the future any of the slaves 10 sets the interrupt request signal on a given bus line 32, the signal from this line through block 8 enters the bus 19 and through element 39 sets the trigger 38. The signal from the direct output of trigger 38 through element 40 bus 47 will arrive as an interrupt request signal (TPD) on bus 2, causing an interruption of the work program of the computer. In the part of the cycle Provision of interruptions of a computer by applying a signal Input to bus 23 (46) prepares the device for inputting an interrupt vector by setting trigger 37. Providing an interrupt grant signal

04268

(SPR) to the bus, 44 causes the interrupt vector to be output from the output of the descrambler 43 to the bus 16 by a signal on. In the code element AND 42. 5 The signal on bus 17 also causes the bus 16 to switch to the output of multiplexer 4 and the I / O signal decoder 7 to form bus 26, which requires the completion of the cycle. 10 After receiving the interrupt vector, the computer in software mode by sequentially polling the state of the VU 10 (cycles Displaying the address of the VU and Reading the register of the state) determines the address of VU 10 that requires service and exchanges data with it.

Thus, the proposed device with less hardware costs provides the exchange of data between computers and peripheral devices in software mode and in the mode of program interruption,

 In addition, the proposed device expands the address space for direct connection of peripheral devices. In particular, the device itself occupies three addresses

30 (in the address space of external computers), and the number of peripheral devices connected to the device is limited only by the size of the data bus and the address register.

FIG L

46

More fsH.

A9resX () j ((shshml I)

HC (bus 90)

SLEEP (tire 22)

Bbifod (bus 23)

Zap. afpecffS (2SI bus

Afpec vu (yt bus}

Sost.vU (bus 3)

From Address given. Address (bus 11} IW (tires a 30)

Si A (bus 22)

CIP (tire 26)

Reading reg. status (tire 27)

%. (comp. WU)

U2.6 Address is given. Address (bus 11) V Data V

HC (tires and 50)

SIA (tire 22)

Bgod (bus 23)

Vgod given. (tire 33)

Data (JO bus)

SIP memory (bus 25)

CIP (tire 26)

FIG. 7

. N

. "

Claims (1)

A device for interfacing a computer with a peripheral input / output device, comprising a decoder, an interrupt unit, a multiplexer, a first and second gain unit, the input-output of which are the first and second inputs and outputs of the device, the first input and output of the interrupt unit the first output and input of the first amplification unit, the second input and output of which are connected respectively to the first ^ Y and second inputs of the decoder, and the third input to the multiplexor output, the first control input Connections to the second output of the decoder, and the first data input with the first output of the second gain block and a second input of the interrupt unit, characterized in that, to reduce hardware expenses, it entered the address register and selector addresses, wherein the third output of the first block efforts ^x Nij connected to the information inputs of the address selector and address register, the first input of the second amplification unit, and the third input of the interrupt unit, the second and third outputs of which are connected respectively to the second information and second To the control inputs of the multiplexer, the control input and output of the address selector are connected respectively to the fourth output of the first amplification unit and the second input of the decoder, the third input and output of which are connected respectively to the third output and fourth input of the interrupt unit, and the fourth input and output, respectively, to the second output and the input of the second amplification unit, the third output and input connected respectively to the third and fourth information inputs of the multiplexer and the output of the address register, the control input Otori connected to the fifth output of the decoder.