SU1557565A1 - Device for interfacing computer and terminals - Google Patents

Abstract

The invention relates to computing and can be used in classes of programmed education and in systems for the collection and processing of educational information. The aim of the invention is to expand the functionality of the device due to the possibility of connecting to the computer of any type of terminal. The device contains a communication unit 1, a group of 2 communication units with terminals, a load unit 3. The device provides communication of a computer with a group of terminals over serial communication channels with a duplex protocol. 1 hp f., 3 Il.

Description

1

The invention relates to computing and can be used in classes of programmed education and in systems for the collection and processing of educational information.

The aim of the invention is to expand the functionality of the device due to the possibility of connecting

cheni to the computer of any type of terminal.

Figure 1 and 2 shows the block diagram of the proposed device; FIG. 3 is a block conversion circuit diagram.

Fig. 1 shows: communication unit 1, a group X of N communication units with terminals, a load unit 3, a group of information input-outputs 4 groups of units 2, a computer 5, a group 6 of terminals.

The communication unit 1 comprises (FIG. 2) the first block 7 of mine formers, the address decoder 8, the code conversion unit 9, the driver of 10 pulses, the third block 11 of bus drivers, the second block 12 of bus drivers.

The terminal 2 communication unit contains (FIG. 2) the first bus driver unit 13, the third bus driver unit 14, the address decoder 15, the second bus driver unit 16, the pulse driver 17, a register.

18 states, 19 shift register, dei

encoder 20 subaddress, register 21 subaddress, first input - output 22 blocks. The code conversion unit 9 comprises (FIG. 3) a counter 23, a pulse generator 24 and a shift register 25.

The device can be divided into two components: a computer with a communication unit 1 and the class itself, which includes units 2 and terminals.

The communication unit 1 is connected to the units 2 via a serial highway. The trunk has one bidirectional data line and two unidirectional lines: the clock signal and the terminal readiness.

The interface operation algorithm provides for a byte exchange of information between computers and terminals. It is constructed in such a way that the initiator of the exchange is a computer.

The communication units 2 with the terminals are reset to a signal by the End of Interchange (QoS) signal transmitted via the Sync line. In the first byte of any exchange, the block 2 group address, the sub device address is transmitted

0

Q 5

,

Q

and a command (input or output), with the three least significant bits being the subaddress of the terminal, the four following ones the address of the interface block, and the last, most significant bit determines the direction of information exchange.

Communication unit 1 is connected with a computer through its address register. The eight lower bits of the register are data, the 9th is the readiness of communication unit 1, the 10th is the readiness of the terminal.

Communication unit 1 operates as follows.

On the backbone of the computer 5, the address of the communication unit 1 is set. The decoder 8 according to the signal received from block 12, fixes the coincidence of the address (CA). The signal CA prepares the communication unit 1 to input or output information.

In the Output mode, the driver 10 by the signal Output generates a recording signal in block 9. The same signal is the start signal. After the start, the code conversion unit 9 generates a series of 8 sync pulses, which is transmitted through block 11 to the highway 22. By the same pulses, the information recorded in the shift register 19 and in the code conversion unit 9 is output to the highway 22 through block 11.

If there is a unit in the bit of information transmitted from the output of block 7, the driver 10 generates a QO signal, which is transmitted to the backbone 22. The recording signal is not generated. On the signal KO unit 9 is returned to its original state. During the code conversion or in the presence of a QoS signal, the driver 10 generates a Signal Invalid signal.

In the Input mode, the block 12 transmits by a signal from the Input coming from the mainline of the computer to the computer 5, the transfer unit 7. 45 Information from the shift register 19 and from block 9 through block 7 is entered into the computer. In either mode, provided

35

the match of the address of the communication unit 1, the unit 7 generates a passive device initialization signal (CIP).

SIL (Input to Output) CA.

Before the exchange begins, a Qo signal is transmitted via trunk 22, through which all units 2 of communication with the terminals are set to idle state. In total, block 2 has three states: Waiting — the block is ready to receive an address; Work - this state is established after address match

block, when choosing the latter; Blocking is a condition in which block 2 does not respond to any signals from trunk 22, except for QoS.

The Qo signal is transmitted over the sync line. line 22 has a pulse of the order of I-10 sync pulse periods and is extracted by a low-frequency filter in the shaper 17. From the line 22, information is fed through block 13 to the input of the shift register 19, in which it is recorded on the trailing edge of the sync pulses.

ten

QoS via line 22. Line 22 ends with a resistor load of 3, which is an agreement of 120 ohms.

Claims (2)

1. A device for interfacing a computer with terminals, which contains a communication unit with a computer, the first input-output of which is connected to the input-output of devices for connection to the information input-output of a computer, and the communication unit with the computer contains the first block of bus In register 19, there is a conversion of 15 drivers, the address decoder of the serial code into the parallel one. The first byte of the information sequence after the signal KO content20 the terminal's subaddress (1-3 bits), the block 2 address (4-7 bits) and the I / O operation code (8 bits) live. After every eighth clock pulse, shaper 17 generates a End of Byte (KB) signal. On the first signal 25, the address of the block is decoded by the decoder 19, the information about the match (mismatch) of the address is written to the state register 18, the subaddress and the I / O operation code are written to the subaddress register 21 and then the unit 2 goes to one of the states The pulse former, in the communication unit with a computer, the information input / output of the first block of bus formers is the first input / output of the communication unit with a computer, the output of the first block of bus formers is connected to the first input of the address decoder, thirty that, in order to expand the functionality of the device due to the possibility of connecting terminals of various types to the computer, a group of communication units with the terminal and a load unit are introduced into it, the second input / output of the communication unit with the computer connected to the input of the load unit and the first inputs -the outputs of the communication unit with the group terminal, the second input-output of the 1st communication unit with the terminal of the group is one or lock. In the Operation mode, the decoder 20 subaddress via block 14 connects to input or output one of the terminal's subdevices to register 19 via the trunk 14, as well as the readiness signal of the subdevice to the line Ready terminal of the highway 22 through block 16. The direction of transmission is determined by the I / O signal in the register 21 sub addresses The reset of the information in registers 21 and 18 of the subaddress and the state occurs on the signal CB. When information is transmitted from block 2 to the computer, the Input signal is transmitted in the first byte of information (one in the highest order,). But at the end of the first byte, block 13 is switched on to transfer information from register 19 to trunk 22. To enter one byte of information from block 2 to a computer, a series of eight synchro pulses is transmitted via the Sync V line. 25 of block 9. The exchange of information with the terminal ends with a signal transmission QoS via line 22. Line 22 ends with a resistor load of 3, which is an agreement of 120 ohms. Invention Formula 1. A device for interfacing a computer with terminals containing a communication unit with a computer, the first input-output of which is connected to the input-output of the device for connecting to the information input-output of a computer, and the communication unit computer contains the first block of bus drivers, address decoder and pulse generator, in which in a communication unit with a computer information input-output of the first block of bus drivers is the first input-output of a communication unit with a computer, the output of the first block of bus drivers is connected to the first input of the address decoder, that, in order to expand the functionality of the device due to the possibility of connecting terminals of various types to the computer, a group of communication units with the terminal and a load unit are entered into it, the second input / output of the communication unit with the computer connected to the input of the load unit and the first inputs -the outputs of the communication unit with the terminal of the group, the second input-output of the 1st communication unit with the terminal of the group the input-output of the device for connecting the information input-output of the i-terminal, with the second, third blocks of bus drivers and the block code conversion, in which in the communication unit with a computer the information input of the second block of bus drivers is connected to the first input-output of the communication unit with a computer, from the first to the fourth the outputs of the second block of bus drivers are connected respectively to the control input of the first block of bus drivers, with the second input of the address decoder, with the first input The pulse former and with the first input-output of the communication unit with a computer, the address of the address decoder is connected to the second input of the pulse generator, the output of the first block of bus driver units is connected to the first information input of the code conversion unit, and the first information output of the converter unit codes is connected to the information input of the first block of bus drivers, the first output of the pulse driver is connected to the first synchronization input of the code conversion unit and with inf the second input of the bus driver, the second output of the pulse driver is connected to the synchronization input of the code conversion unit and the sample input of the third bus driver unit, the first, second information inputs of which are connected to the second, third information output of the code conversion block, synchronization output and whose second information input is connected to the fourth input of the pulse generator, respectively, with the information output of the third busbar unit x drivers, the third output of which is connected to the input of the resolution of the code conversion unit, the input-output of the third block of bus drivers, and the fifth input of the pulse generator are the second input-output of the computer, each communication unit with a terminal group containing first to third blocks of bus drivers, pulse generator, shift register, subaddress register, status register, address decoder and subaddress decoder, and in the communication unit with the group terminal information input-output of the first unit the bus drivers and the output of the second block of bus drivers are the first input-output of the block, the information input of the third block of bus drivers, the output of the sub address decoder are the second input-output of the communication unit with the terminal and connected to the first information input of the second block of bus drivers, the output of the status register is connected to the first input of the sub address decoder and to the second information input of the second block of bus drivers; the first output of the pulse driver is connected to the input b shift register synchronization and is connected to the second input-output of the communication unit with the terminal, the first information output of the first block of bus drivers is connected to the first information input of the shift register and to the input 0 five 0 five 0 five 0 five pulse generator, the second output of which is connected to the information input of the status register and the first input of the address decoder, the second input of which is connected to the first information input of the shift register, to the synchronization input of the subaddress register and to the information input of the third block of bus drivers, whose input and input the samples of the first block of bus drivers are connected to the first output of the subaddress register, the second output of which is connected to the second input of the sub address decoder, the output of the address decoder connected to the synchronization inputs of the status and subaddress registers, the second information output of the shift register is connected to the second information input of the first block of bus drivers, the second information output of which is connected to the second information input of the shift register, the third information input of which is connected to the output of the third block of bus drivers, the third the output of the pulse driver is connected to the enable input of the status register. 2. The device according to claim 1, characterized in that the code conversion unit comprises a pulse generator, a shift register and a counter, wherein the input and output of the parallel data of the shift register are respectively the first information input and output of the block, the control input and output of the serial data of the register the shift are respectively the block resolution input and the second information output of the block, the output of the pulse generator is connected to the synchronization input of the counter, to the first synchronization input of the shift register and is output the block synchronization house, the write enable entries of the counter and the shift register are the first synchronization input of the block, the second synchronization input of the shift register is the second synchronization input of the block, the information input of the counter is the second information input of the block, the output of the counter is connected to the lock input of the pulse generator and c the third informational output of the block.