SU1679494A1 - Interface unit for communication of the subscriber over the bus - Google Patents

Abstract

The invention relates to computing and can be used to provide data exchange between computers. The aim of the invention is to expand the field of application of the device. The device contains a universal synchronous asynchronous transceiver, address decoder, two counters, clock generator, three OR elements, two data buffers, a register, four triggers, a comparison circuit, four single vibrators, eight And elements, a trunk receiver and a transmitter. 2 Il.

Description

. The invention relates to computing and can be used to facilitate the exchange of information between computers.

The aim of the invention is to expand the field of application of the device.

FIG. 1 is a functional diagram of the device, and FIG. 2 shows a scheme for integrating a computer into a system.

The device (see Fig. 1) contains a reversible parallel-to-serial code converter (universal synchronous-asynchronous transceiver-USAP) 1, made, for example, on the basis of BIS 580B B51, decoder 2 addresses, counter 3, 4 clock pulse generator, OR element 5, bus driver (data buffer) 6, device address input line 7, information device output parallel code line 8, device record input line 9, device initial setup line 10, counter 11, register 12, triggers 13-16, circuit diagram 17, one-shot 18-21, elements AND 22-29, elements IL 30 and 31, bus driver (data buffer) 32, trunk transmitter 33 and receiver 34, device read input line 35, device interrupt output line 36 and line 37 information input-output serial code.

The integration of subscribers (computers) 38 into the system through trunk lines 37 of the proposed devices 39 and 40 is shown in FIG. 2

The device works as follows.

The exchange of information between the computer source 38 and the computer receiver 38 using devices 39 and 40 includes the following steps (Fig. 2):

1. The initial installation of devices 39 and 40 of the system is carried out from their computers through lines 10. By impulse in lines 10 in each device 39, 40, the USART 1 is installed and set to zero

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Triggers 13, 15, 16, as well as counter 11. Triggers 14 are reset to zero by a positive pulse at the output of the one-shot 21.

2, The recording of control information in the UCARD 1, In the corresponding registers of the UCCA 1, instructions of the asynchronous exchange mode and instructions of commands are recorded. In this case, device 39 is programmed as a transmitter, and devices 40 as receivers. The information is recorded in USART 1 at the address specified on line 7, and is synchronized by the write pulses on line 9. At the same time, the logical zero signal is received by the address decoder 2 via element 22 at the input of the USART 1. The same signal opens the data buffer to receive 6 and the information with line 8 enters the data channel of the USART 1.

3, The recording of the first data word in the ULAB 1 is carried out similarly to the process described above. The selection of USCA 1 registers is carried out by feeding a logical zero in the low-order section of line 7, which is fed through AND 23 to the USART 1 of device 39. The first data word contains information about the address of information receiver 40. Issuing information from the USART 1 transmitter 37 is carried out automatically after data is recorded through element 28 and the main transmitter 33. After the data word is applied to the line at the end of the transmission. The USARP 1 transmission ends with a signal on the front of which the trigger is set to one. , thereby submitting from its inverse output a zero level to the input of data buffer 32. The source computer 38 goes into a cyclic polling mode of the state of this trigger by reading it along line 8. The reading is performed at the address on line 7 and is synchronized by pulses on line 35 This signal at the output of the element OR 30 produces a negative pulse, opening data buffer 32 for transmission.

4, Addressing device 40 from line 37 from source device 39 is performed by an address word transmitted via line 37. The address word from line 37 goes through the OR 31 element to the USRT 1 receiver input of all devices 39 and 40. After this word arrives at the output A high-level signal appears at the ready state of USAP 1, on the front of which the trigger 16 is set to one and according to which the trigger 14 of all devices 39 and 40 is set to one. On the leading edge of the signal from the output of the trigger 16, the output of the single-oscillator 19 appears a pulse that goes through; elements (And 22 and 23 goes to the control inputs of the USART 1. And on the leading edge of this signal at the output of the one-shot 18, a negative polarity pulse appears, which through the elements of the 24 goes to the read inputs devices of system 39 and 40. This pulse is nested with respect to the pulse per

0 output elements And 22 and 23. Thus, the output of the received address word to the data channel of the USART 1. The read address word is fed to the inputs of the secondary circuit 17, the second inputs of which are connected to the outputs of the register 12. On register 12, a fixed set of logical zeros and units, the address of the receiver device 40 is set on line 37.

When data coincides with the content

0 register 12 at the output of the comparison circuit 17, a single potential is formed, which is fed to the information input of the trigger 13. On the falling edge of the read pulse from the one-shot 18, the trigger 13 switches to the state of the logical unit, which enters the computer-receiver 38 and transfers its data reading mode, Reading data from USART 1 is similar to the writing process. The signals do not come through line 35 from computer receiver 38 through element I 24 to the input of USRP 1 of the corresponding device 40. USRAP 1 data register is addressed through line 7 of the address, which leads to the appearance of corresponding signals at its input and mode. On the read pulse, information is output to the data channel of the USART 1, which through the buffer

0 data 6, opened for transmission by a read pulse, arrives at line 8. At the falling edge of the pulse at the output of the element OR 5 in the addressed device 40, at the output of the one-shot 20, a negative pulse appears, which through element 28 and the trunk transmitter 33 enters line 37 and through trunk receiver 34 enters all devices 39.40 of the system. A trigger 14 is zeroed on the falling edge of this pulse. The same pulse in transmitter 39 zeroes trigger 15. The pulse does not arrive at the USART-1 receiver input in devices 39, 40, because at the time of its passage the elements OR 31

5 are closed by a high level coming from the output of the trigger 14.

5. Transfer the next word. The computer transmitter 38, reading in the polling mode the logical unit of the trigger 16, proceeds to the issuance of the next word. The transfer is carried out similarly to the issuance of the address

information. After transmitting on the leading edge of the signal, the trigger 15 switches to the state of a logical unit, thus a logical zero signal appears at the input of data buffer 32. The computer source 38, after transmitting the next word, enters the cyclic polling mode of the trigger 15. The transmission of the next word is possible upon the arrival of a confirmation pulse, which will reset the trigger 15 to zero.

6. Receive another word. The computer receiver 38, which, after being addressed to the information reading mode, is in the state of polling the readiness signal of the USART 1 by reading its state register. The status register is addressed via line 7. The read cycles are synchronized by pulses on line 35. After receiving the next word, a signal of a logical unit appears on the readiness output output of the USART 1, which is set to one trigger 14. The logical unit appears in the corresponding bit USART 1 state register of device 40. Computer receiver 38 reads the received word from USART 1 data register through data buffer 6, which is open for transmission by sampling signals from address decoder 2 and reading from line 35. On a read pulse, remove The signal from the readiness output of the USAP device 1 of the device 40. After the information is cleared, the receiving device 40 sends to the line 37 through the element 28 and the main transmitter 33 a confirmation pulse, on the front of which the trigger 14 zeroes in this device and in the source device 39 trigger 15. The transfer process can be continued.

Thus, the transmission is performed by the source after acknowledgment of receipt by reading the status of trigger 15, and reception by analyzing the readiness bit of the USRT 1 state register of receiver 40.

7. Finishing the transfer and resetting the system. Before the system starts operation, the counters 11 are reset to the initial state by the logic zero level at the trigger output 16. After all the devices of the system 39, 40 receive the address information, the counters 11 of these devices switch to the counting mode by one from the trigger 16. When transmitting information on lines 37 counters 11 are nullified with confirmation signals on line 37. If during a certain time interval there is no information transfer on line 37, then the transfer outputs of counters 11 in all devices of the system

39, 40 a transfer pulse appears. This pulse arrives at the inputs of the sample and the USRT mode 1, and also blocks the operation of the comparison circuits 17. On the leading edge 5 of this pulse, a negative pulse appears at the output of the one-shot 18, which leads to the forced reading of information from the USART 1. The process is similar to addressing , only searching for switching to the unit of flip-flops 13. During this reading, the readiness signals of the USRT receiver 1 in non-addressed devices 40 are removed. On the trailing edge of the transfer signal of the counter 11 at the outputs of the one-vibrator are formed and pulses which are reset to zero triggers 13, 14 and 16, and are set in the initial state counters 11 in all the devices 39,40. The transmission of information from source computer 39 may be continued. The readiness signal for transmission is the state of the trigger 16, which is polled by the source computer 38 in the same way as the trigger 15.

Claims (1)

5 claims A device for interfacing a subscriber with a trunk, containing a reversible converter of a parallel code into a serial one, the entry of which is 0 is the device's recording input, and the information input-output of the parallel code is connected to the first information input-output of the first bus driver, the second information input 5 whose output is the information input-output of the parallel device code, eight AND elements, three OR elements. four triggers, first counter, clock generator, output connected to the counting input of the first counter and the clock input of the reversible parallel code-to-serial converter, the receive and transmit synchronization inputs of which are connected to the output 5 of the first counter, and the reset input is the input of the initial setup of the device, and the address decoder, the input of which is the address input of the device, and the first output is connected to the first inputs of the first 0 elements AND and OR, and the input of the sample of the reversible parallel code to serial converter is connected to the output of the first AND element, characterized in that, in order to expand the area 5 applications / devices, a second counter, a second bus driver, a comparison circuit, a register, four one-oscillators and a trunk receiver and a transmitter are inputted into it, the second output of the address decoder is connected to the first input the second OR element, the second input of which is the input of the device and is connected to the direction input of the first bus driver, the sample input connected to the first output of the address decoder, the inputs of the read mode and the serial data code of the reversible parallel code converter into the serial one are connected respectively to the outputs of the second and the third element And the third element OR, the output of the fourth element And is connected to the second input of the first and the first input of the second element And through the first Bottom vibration - with the first input of the third element I and the synchronous input of the first trigger, the output of which is the output of the device interruption, the output of the second trigger connected to the first input of the third OR element, the second input connected to the output of the main receiver, the reset input of the second counter, the synchronous input of the second trigger and the first the input of the fifth element And, the second input of which is connected to the first input of the sixth element And and the input of the initial installation of the device, and the output - to the reset input of the third trigger, inverse outputs three the second and fourth triggers are connected to the corresponding information inputs of the second bus driver, the outputs of which are connected to the information input / output of the parallel device code, and the sample input with the output of the second OR element, the output of the main transmitter and the input of the main receiver, form the input-output serial device code, the direct output of the fourth trigger is connected to the reset input of the first trigger, the installation input of the second counter and through the second one-shot - with the first input of the fourth element And, the input of the main transmitter is connected to the output of the seventh element And, the first input of which through the third one-shot is connected to the output of the eighth element And, the first and second inputs connected respectively to the outputs of the first element OR and the first trigger, whose information input connected to the output of the comparison circuit, the first information input of which is connected to the output of the register, and the prohibition input - to the output of the second counter, the second input of the fourth element I and the first start input of the fourth one-oscillator, the second start input and the first and second outputs of which are connected respectively to input the initial installation of the device, the second input of the sixth element And and the reset input of the second trigger, the output of the sixth element And is connected to the reset input of the fourth trigger; are connected respectively to the second information input of the comparison circuit, to the second input of the seventh element I, to the synchronous input of the third trigger and to the installation input du second flip-flop and the fourth flip-flop clock terminal, the second the inputs of the first OR element and the third AND element are connected to the reading input of the device, the third input of the first OR element and the second input of the second AND element are connected to the address input of the device.