SU798784A1 - Device for interfacing computer with control units - Google Patents

Description

(54) DEVICE FOR COUPLING COMPUTING MACHINE WITH CONTROL OBJECTS

The invention relates to computing, in particular, to input / output control devices that communicate with computers with control objects.

Control devices of a computer system are known in the form of specialized communication circuits with peripheral devices, including a computer communication unit, an input unit, an output unit, a mode setting unit 1.

The disadvantage of these devices is their limited scope due to the presence of hardware I / O units, which even with minor modifications of the peripheral device cannot be used.

The closest in technical essence to the present invention is a parallel input-output device that provides programmatic access to registers and contains a clock counter, multifunctional information input-output registers, providing the ability to change the direction of transmission, transfer data with or without storage in synchronous or asynchronous mode and connected to the controlled object and through the data highway - computers, control registers connected at the outputs to the multifunctional registers, and inputs - with a data highway, a read / write control unit connected to the inputs with control computer buses, and output to the corresponding inputs from the multi-O function I / O registers and control registers 2.

A disadvantage of this device is its limited functionality, since it does not allow peripheral devices to be connected to the computer, which has serial input / output information.

The purpose of the invention is to expand the functionality of the device by providing the possibility of combining parallel and serial I / O.

The goal is achieved by the fact that the device containing

5, four transmit-receive registers, the first inputs-outputs of which are the first group of inputs-outputs of the device, two control registers, the first inputs of which are connected 0 to the device data highway and

nepBfcviM input data buffer memory, a clock counter and a communication unit with a computer, the group of input-output of which is the second group of input-output devices of the device, and the first output is connected to the second inputs of the control registers and the buffer data memory connected by the input- output with the second input-output of the fourth transfer-reception register, the group of inputs of which is connected to the first group of outputs of the second control register, the second group of outputs of which is connected to the group of inputs of the third register of reception-feather cottages, first and second groups of outputs of the first control register are connected respectively to groups of inputs of the first and second transfer-reception registers, the second inputs-outputs of which and the second input-output of the third transfer-reception-transfer register are connected to the device data line, the interrupt unit is entered The address selection block and the control signal generation block, the first and second groups of inputs of the interrupt blocks being the first and second groups of control inputs of the device, respectively, and the output is the output of the device, groups the inputs of the address selection block are a group of address inputs of the device, a group of outputs connected to the third inputs of control registers and a buffer data memory, the inputs of the first, second and third registers of reception-transmission and the first input of the fourth reception-transmission register, and input the second output of the communication unit with the computer, the group of outputs of the second control register is connected to the group of inputs of the control signal generation unit and to the first input of the clock counter, the second input connected to the input m sync pulses of the device and the first input of the control signal generation unit, the first and second outputs of which are connected respectively to the second and third inputs of the fourth transmission-reception register; the third and fourth outputs correspond to the fourth input of the buffer memory and the input of the interrupt block, respectively, and the second input to the output of the clock pulse.

In this case, the control signal generation unit contains eight AND elements, three OR elements and a delay element, the output of the first AND element being connected to the first input of the first OR element, the first input to the first inputs of the second and third AND elements, the second input the first inputs of the fourth and fifth elements And and the first input of the block, and the third input - with the first inputs of the sixth and seventh

AND elements and the first input of the second OR element, the output of which is the second output of the block, and the second input connected to the output of the second AND element, the second input connected to the fourth output of the block, the second input of the seventh element and the output of the fifth AND element, the second input of which The second input of the block, the second input of the fourth element AND is connected to the third input of the seventh element AND, the output connected to the first input of the third OR element, the output of which is the third output of the block, the second input connected to the output of the third O and the first input of the eighth And elements, and the third input with the output of the sixth element And, the second input of which is connected to the output of the fourth element And and the second input of the first element OR, the third input connected to the output of the eighth element And, and the output with the first output of the block, the second inputs of the third, eighth, fourth, and first, third inputs of the first And elements are the inputs from the group of inputs of the block.

In addition, the interrupt block contains two triggers, the OR element and the AND element, the first input of the AND element connected to the output of the OR element, the group of inputs and the input of which are respectively the second group of inputs and the input of the block, the output of the first trigger is the output of the block, and the first input is connected to the output of the element And, the second input connected to the output of the second trigger, the first and second inputs of which and the second input of the first trigger are connected to the corresponding inputs of the first group of block inputs, the third inputs of the trigger are connected to eml hydrochloric unit bus.

The address selection block contains a comparison circuit and an address decoder, the first inputs of which are connected to the block input group, the second input of the comparison circuit is the block input, and the output is connected to the second input of the decoder, the output group of which is the block output.

FIG. 1 is a block diagram of the device; in fig. 2 is a functional block diagram of the formation of control signals and interrupts; in fig. 3 - a functional diagram of the address address block.

The device contains registers 1-4 of reception and transmission, a buffer memory 5 of data, a block of forming control signals, a block 7 of interrupts, control registers 8 and 9, a block 10 of communication with a computer, an address selection block 11, a counter 12 clock pulses , output 13 of the device, outputs 14 of the first group of inputs, vtorp

a group of device inputs 15, a data line 16, inputs 17 of an address group of inputs, inputs 18 of the second group of inputs, inputs-outputs 19-22 of the second group of device inputs-outputs, input 23 of clock pulses.

The control signal generating unit b (Fig. 2) contains elements OR 24-26, elements AND 27-34, and element 35 delays. Block 7 interrupt includes the element OR 36, the element And 37 and. the triggers 38 and 39, and the address selection block 11 (FIG. 3) is the comparison circuit 40, the address decoder 41, the input 42 and the output 43 of the output group of the block.

The device works as follows.

In the sequential synchronous input mode, data from the controlled object is fed to the second input of the multifunction register 4, with each bit of information being accompanied by a clock pulse entering through the input 23, the elements AND 37, 34, OR 24 per register 4. On the register, the serial data is converted into parallel bytes. Every eighth sync pulse arriving at the input of counter 12 sets the latter to the zero state, moreover on the falling edge. the sync pulse using the elements AND 31, 33 and through the OR element 26 at the input of the buffer memory 5, a positive differential is formed, according to which the information in parallel form from register 4 is rewritten in the memory buffer 5 and stored in it. The computer, address to buffer memory, reads the information.

In the mode of sequential synchronous output, if there is a positive pulse, the corresponding output of the control register 9, which provides connection of the buffer memory 5 to the computer, is used to write data from the computer to the buffer memory synchronously with the positive edge of the signal from the output of the OR 26 element to the buffer memory. On register 4, parallel information is converted into serial synchronously with a positive differential signal at the output of element 24, which is formed by element 27 and element 35 of Derzhko of negative differential clock.

Every eighth clock pulse, which sets the counter 12 to the zero state, forms AND 31 and 28 and OR 25 element a high signal level at the corresponding input of the register 4, which allows parallel reception of information from the buffer memory to the register 4 at the element output. OR 24.

In the parallel synchronous input mode, data from the controlled object is transferred to register 4 to the positive edge at the output of the OR 24 element formed through AND 30.

The negative front of the sync pulse through the elements And 30, 32 and the element Q OR 26 forms at the input of the buffer memory 5 a positive signal differential, in which the data from the register 4 are recorded in the buffer memory. The reception of information in the computer from the buffer memory 5 is carried out at a high

5 the level of the signal at the output of the control register 9 arriving at the first input of the And 29 element.

In the parallel synchronous output mode, data from a computer on the same

0, the control register 9 signal is stored in the buffer memory, and the negative edge of this signal is recorded in register 4, because the output of the OR 24 element

5, elements 20 and 34 form a positive write control signal differential.

In operation, unit 7 generates a computer interrupt signal when signals are received at one of inputs 18 from controlled objects or from output of element 31. Decoder 41 generates a control signal to enable operation using the corresponding address code at its input and control input to output circuit 40 comparison.

- Thus, the device provides the exchange either in parallel codes or in sequential ones, which is

0 ultimately reduces the hardware cost of the computing system.

Claims (4)

Invention Formula A device for interfacing a computer with control objects, containing four reception-transmission registers: the first inputs / outputs of which are the first group of inputs and outputs of the device, two control registers, the first inputs of which are connected to the data highway of the device and the first input buffer data memory, a clock counter and a communication unit with a computer, the input-output group of which is the second group of input-output devices of the device, and the first output is connected to the second inputs of control registers and the buffer data packet connected by the input-output to the second input-output of the fourth transmission-reception register, the group of inputs of which is connected to The first group of outputs of the second control register, the second group of outputs of which is connected to the group of inputs of the third reception-transfer register, the first and second group of outputs of the first control register are connected respectively to the input groups of the first and second reception-transmission registers, the second input-outputs of which and the second input-output of the third reception-transfer register is connected to the device's data line, which is characterized by the fact that, in order to expand the functionality of the device by providing exchanging parallel-to-serial codes, an interrupt block, an address selection block and a control signal generation block are entered into it, the first and second groups of inputs of the interrupt blocks being the first and second groups of device control inputs, respectively, and the output is the output of the device, a group of inputs The address selection block is a group of address inputs of the device, a group of outputs is connected to the third inputs of control registers and the buffer data memory, the inputs of the first, second and third reception-transfer registers and the first input of the fourth reception-transfer register, and the input to the second output of the communication unit with the computer, the output group of the second control register is connected to the input group of the control signal generation unit and to the first input of the clock counter by the second input of the device connected to the input clock and the first input of the control signal generation unit, the first and second outputs of which are connected respectively to the second and third inputs of the fourth reception-transmission register, the third and even Yield ertye - respectively to the fourth input of the buffer memory and the data entry unit interrupts, and the second input to the output of clock counter. 2. The device according to claim 1, wherein the control signal generation unit comprises eight AND elements, three OR elements and a delay element, with the output of the first element AND through the Delay element connected to the first input of the first OR element, the first input to the first the inputs of the second and third elements And, the second input with the first inputs of the fourth and fifth elements And And the first input of the block, and the third input with the first inputs the sixth and seventh And elements and the first input of the second OR element, the output of which is the second output of the block, and the second input connected to the output of the second And element, the second input connected to the fourth output of the block, the second input of the seventh And element, and the output of the fifth And element, the second input of which is the second input of the block, the second input of the fourth element AND is connected to the third input of the seventh element AND, the output connected to the first input of the third OR element, the output of which is the third output of the block, the second input It is single with the output of the third and first input of the eighth element AND, and the third input with the output of the sixth element AND, the second input of which is connected to the output of the fourth element AND and the second input of the first OR element, the third inlet connected to the output of the eighth element And, and the output - with the first output of the block, the second inputs of the third, eighth, fourth and first, third inputs of the first element And are the inputs from the group of inputs of the block. 3. The device of claim 1, wherein the interrupt block contains two flip-flops, the OR element and the AND element, the first input of the AND element connected to the output of the OR element, the group of inputs and the input of which are respectively the second group of inputs and the input of the block, the output of the first trigger is the output of the block, and the first input is connected to the output of the element I, the second input connected to the output of the second trigger, the first and second inputs of which and the second input of the first trigger are connected to the corresponding inputs of the first group of inputs of the block, t and trigger inputs are connected to an earth bus unit. 4. The device according to claim 1, wherein the address selection unit comprises a comparison circuit and an address decoder, the first inputs of which are connected to the group of inputs of the block, the second input of the comparison circuit is the input of the block, and the output is connected to the second input of the decoder, the output group which is a group of block outputs. Sources of information taken into account in the examination 1. USSR author's certificate No. 497576., cl. G About F 3/04, 1973. 2, Tarrow et al. Supercomponent: a computer on the same board with programmable input-output interfaces. - Electronics, 1976, No. 3, (prototype).