RU1798791C - Device for interface connection - Google Patents

Abstract

The invention relates to the field of computer technology and can be used to connect peripheral devices to computers (e.g., PCs) having an output interface interface C2. The aim of the invention is to simplify the device. The device contains transmit and receive elements, address registers, registers, a clock, a pulse shaper, pulse dividers, triggers, AND, AND-NOT elements, delays, an initial reset node. 3 ill.

Description

The invention relates to computer technology and can be used to connect peripheral devices to electronic digital machines (e.g., personal computers) having a C2 interface output interface (RS-232C).

The purpose of the invention is to simplify the device.

This goal is achieved in that the interface interface device, comprising buses of the first and second interfaces, information reception and transmission elements, first and second address registers, a clock generator, contains five registers, a delay element, a pulse shaper, two pulse number dividers, s .first fifth triggers, the OR-NOT element, the five OR-NOT elements, the initial reset node, the output of the clock generator is connected via the AND element to the input of the first of the series of pulse dividers; the output of the second AND element is connected through the delay element AND and the OR element is NOT with the R-input of the RS-trigger and the first and second registers.

The output of the first divider is connected to the C-input of the third and fourth registers and to the C-input of the second, third and fourth triggers, the output of the second divider is connected to the inputs of the elements AND, starting from the second, with the input C of the fifth trigger and second register, the outputs of the elements AND starting from the second, connected to the inputs C of the first and fifth registers of the first and second address registers, a single output of the RS-flip-flop is connected to the input of the driver and the input of the first element And, the output of the driver is connected to the input S of the fifth trigger and through the first AND-NOT element with the input R of all dividers and the second input of the OR-NOT element. The output of the receiving element is connected to the input S of the RS-trigger, with the D-input of the second trigger, the output of which is connected to the DR-input of the third register, the outputs of which are connected to the internal bus of the device, which is connected to the inputs of all bits of the address registers and In | WITH

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of the first and fifth registers, the outputs of the address registers and the four least significant bits of the first register go to the address buses of the second interface, the outputs of the first and fourth inputs of the register go to the data buses of the second interface, the outputs of the high-order bits of the first register go through AND elements -NOT, starting from the second, onto the control bus of the second interface. The output of the initial reset circuit is connected to the input of the first AND-NOT element, the high-order output of the fourth register is connected to the input D of the third trigger, the output of which is connected to the D input of the fourth trigger, whose inverse output is connected to the input of the transmission element, the output of which is connected to the output devices, the input of the receiving element is connected to the input of the device, the output of the third element AND is NOT connected to the installation input in the unit of the third trigger and with the input for allowing the parallel code to be received in the fourth register, the output of the fourth element I-IE is connected to the third input of the translation state of the fifth register, the output of the fifth flip-flop coupled to the input of the second register, the conclusions of which are connected to inputs of AND gates, starting with the second.

In addition, five registers, a delay element, a pulse shaper, two pulse number dividers, an OR-NOT element, five AND-NOT and AND elements, an initial reset circuit, three Dt-flip-flops, one RS-flip-flop, are installed into the device into the unit of which the passage of clock pulses to the input of the dividers of the number of pulses is allowed, which determine the synchronization of the reception of the code and the issuance of the code and determine the time of the output of the control signals. This makes it possible to communicate with a computer with a C2 interface and a peripheral device with an I 41 interface without using an additional communication microprocessor and RAM and ROM servicing it in the interface device and can significantly reduce the number of equipment by more than 10% ,

Structural diagram of the device shown in figure 1; time chart - in figure 2 and 3.

The interface interface device comprises elements for receiving 1 and transmitting 2 information, the first and. second registers hell. Resa 3 and 4, clock 5, registers 6-10, delay element 11, pulse shaper 12. dividers for the number of pulses 13, 14, triggers 15-19, element OR NOT 20, five elements NOT 21-25, and And 26-30, the initial reset node 31.

The output of the clock generator is connected 5 through the element And 26 to the input of the first divider of the number of pulses 13, the output of the second element And 30 is connected through the delay element 11 and the element OR NOT 20 with the reset inputs of the trigger 15 and registers 8, 10, the output 32 of the first divider 13 is connected with the sync inputs of the third 6 and fourth 9 registers and the second 16, third 17 and fourth 18 triggers, the output 33 of the second divider 14 is connected to the inputs of the elements And 27-30, with the clock inputs of the fifth trigger 19 and the second register 10, the outputs 35-38 of the elements And 27-30 connected to the sync inputs respectively about registers 3, 4, 7, 8, a single output of the trigger 15 is connected to the input of the driver 12 and the input of the element And 26, the output 44 of the driver 12 is connected to the input S of the trigger 19 and through the AND-NOT 21 element with the reset input of the dividers 13, 14 and the second input of the OR-NOT element 20, the output of the reception element 1 is connected to the input of the trigger 15, with the input of the trigger 16, the output of which is connected to the input of the register 6, the outputs of which are connected to the inputs of all bits of the registers of address 3, 4 and registers 7, 8; the outputs of the address registers 3, 4 and the four least significant bits of the register 8 are sent to the address bus address of the second interface, the outputs of the register .7 and the inputs of the register 9 are sent to the data bus of the second interface, the high-order outputs of the register 8 are received through the AND-NOT elements 22-25 on the bus 39-42 of the control signals of the second interface: the output of the initial reset node 3.1 is connected to the input of the AND-NOT element 21, the output of the high-order bit of register 9 is connected to the input of the trigger 17, the output of which is connected to the input of the trigger 18, whose inverse output is connected with input element pere dacha, the output of which is connected to the output of the device 45, the input of the reception element is connected to the input of the device 46, the output 40 of the AND-NOT element 23 is connected to the input of the unit in the trigger unit and to the enable input for receiving the parallel code in register 9, the output 41 of the AND-NOT element 24 is connected to the input of the transfer to the third state of the register 7, the output of the trigger 19 is connected to the input of the register 10, the outputs of which are connected to the inputs of the elements And 27-30.

The device operates as follows.

When the supply voltage is turned on (see; Figs. 1-3), a negative pulse is supplied to the input of the AND-NOT 21 element from the initial reset node 31 and at the output of the element 21. there is a high potential, which sets the dividers 13. 14 and the registers 8. to zero. 10. Upon arrival, the input 46

of the device of the first start pulse (moment 10, positive pulse) at the output of element 1, a low level appears, which sets the trigger 15 to a single state. On the leading edge of the positive edge, a shaper 12 is triggered at its input, the output of which is a narrow negative pulse, which sets the trigger 19 to unity, and also, passing through element 21, sets the dividers of the number of pulses 13, 14 to the zero state and, going through element 20 confirms the state of zero registers 8, TO. The high potential from the output of the trigger 15, entering the input of the element 26, allows the passage through this element of pulses from the generator 5 to the input of the divider 13. The divider 13 starts to count the pulses. After the output appears, the divider 13 at the moment T1 has a positive pulse, it enters the input C of trigger 16 and register 6, and the first bit of the code (start bit) is stored on the leading edge of the pulse in trigger 16. Then, at time T2, the information from the trigger 16 is rewritten from the trigger 16 to the low order of register 6 at the leading edge of the positive pulse at the output of divider 13 and the next bit is received into trigger 16 (the first information bit), i.e. when each subsequent pulse appears at the output of the divider 13, the next bit of information is stored in trigger 16, and the previous one is overwritten in register 6 and shifted in it by one bit from the lower to the highest bits. When the 10th pulse appears at the output of the divider 13, there will be 8 bits of information in register 6 (suppose that an asynchronous mode of operation with a word length of 8 bits was used to transmit interface C2 without parity - oddness).

Suppose that it is necessary to read the code with the memory cell of the address 0105H, and then send the code 89H to this cell (the letter H indicates that the code is hexadecimal). In this case, at time T10, the RAS code inverse to 05H code will be located in register 6, since the code is issued in inverse form (the lower 8 bits of the cell address) to the address and data buses (as in the standard AND 41 interface). After the tenth pulse (moment T11) has finished at the output of the divider 13, the first positive pulse appears at the output of the divider 14, which is fed to the clock input of the trigger 19 and the register 10 and to the elements 27-30. At the output 35, a positive pulse appears, which allows the reception of code 05 from the output of register 6 to register 3. Then, at the next time points (from T11 to T21), the FEH serial code arriving at input 46. inverse to the code 01 N (high order bits of the address), is stored in register 6. After the 20th pulse ends at the output of the divider 13, the second positive pulse appears at the output of the divider 14 at the time T22, which passed through element 29 (since the second input of element 29 at this moment is high potential), it allows the reception of the FEH code from the output of register 6 to register 4.

Then, similarly, at intervals T23 through T32, the sequential FFH code is inverted, the code is inverse to 00 (the third byte code doesn’t matter in reading mode), register 6, and then it is written to register 7.

Then similarly at time with

0 T34 through T43 is stored in register 6, the serial code 2FH, coming to input 46. In the fourth byte, the high order bits of the address and control signals are transmitted. At the end of the fortieth pulse at the output

5 of divider 13, the moment T44 is the fourth positive pulse at the output of divider 14, which, passing through element 30, allows the reception of the 2HN code from the output of register 6 to register 8, as well as the output of

0 read control signal element 24. Thus, at moment T44, a negative pulse is emitted onto bus 40, which sets trigger 18 to the unit and through which a code is received from data buses

5 peripheral device in register 9,

The transmission of the received code, for example, 55Н, occurs when the next 10 pulses are received at input 46 (the first start, eight information and one stop

0 bit).

Suppose, then, it is necessary to issue the ZZN code (inverse of the SSN code) to the same cell with the address 0105H, then then, in the same way, they are sent sequentially in the same way

5 low order bits of the address (moment T49-T59), high order bits of the address (T59-T70), data (T70-T8T), the code in the four low order bits of which is the most high order address bits, and in the four high order bits - 4 (moment

0 T81-T). Code 4 in the most significant bits of the 4th byte indicates that the recording mode is in progress. The code is transmitted from the peripheral device received to the device at the time of T44 via the 1/141 interface at instant T49-T60.

2 and 3, the numbers 10-1, 10-2, 10-3 10-4 denote the outputs of various bits of the register 10.

The input of the register 9 and the input of the trigger 19 are connected to the bus of the housing and therefore, when the clock pulses arrive at the input from these devices, the zero code is sequentially entered.

Claims (1)

SUMMARY OF THE INVENTION A device for interfacing interfaces, comprising buses of the first and second interfaces, information receiving and transmitting elements, first and second address registers, a clock generator, which, in order to simplify, contains five registers, a delay element , pulse shaper, two pulse number dividers, five triggers, the OR-NOT element, the five AND-NOT elements and the five AND elements, the initial reset unit, the output of the clock generator is connected to the first input of the first AND element, the output of which is connected to the input ohm of the first pulse number divider, the output of the second AND element is connected through the delay element to the first input of the first OR-NOT element, the output of which is connected to the reset inputs of the first trigger, the first and second registers, the output of the first pulse divider is connected to the sync inputs of the third and fourth registers, of the second, third and fourth triggers, the output of the second pulse divider is connected to the first inputs from the second to fifth elements AND, the clock of the fifth trigger and second register, the outputs of the second rio fifth ele ntents are connected to the sync inputs of the first, fifth registers, first and second address registers respectively, the single output of the first trigger is connected to the input of the pulse former and the second input of the first element And the output of the pulse former is connected to the installation input of the fifth trigger and the first input of the first AND -NOT whose output connected to the reset input of the first and second pulse number dividers and the second input of the OR-NOT element. the output of the receiving element is connected to the installation input the first trigger, with the data input of the second trigger, the output of which is connected to the data input of the third register, the outputs of which are connected to the data inputs of the first and second address registers, the first and fifth resisters, the outputs of the first and second address registers and the four least significant bits of the first register are the output addresses of the device, the outputs of the fifth and the data inputs of the fourth register are the input-output of the data of the device, the high-order outputs of the first register are connected to the first inputs from the second to fifth elements AND NOT the odes of which are the control signal outputs of the device, the output of the initial reset node is connected to the second input of the first AND-NOT element, the output of the high order of the fourth register is connected to the data input of the third trigger, the output of which is connected to the input data of the fourth trigger, the inverse output of which is connected to the input of the transmission element, the output of which is connected to the output of the device data, the input of the reception element is connected to the data input of the device, the output of the third AND-element is NOT connected to the installation input in 1 of the third trigger and to the enable input for receiving the parallel code of the fourth register, the output of the fourth element IS NOT connected to the input transfer to the third state of the fifth register, the output of the fifth trigger is connected to the data input of the second register, the outputs of which are connected to the second inputs of the second to fifth elements I.