SU1564628A1 - Device for simulation of computer failures and malfunctions - Google Patents

Abstract

The invention relates to computing and is intended to simulate faults in an experimental study of the reliability and stability of the operation of structurally redundant computing systems built using various asynchronous backbone interfaces. The purpose of the invention is to expand the functionality of the device by simulating faults in the "address" and "data" cycles of the computer main. Device 1 includes memory blocks 16, 17, encoder 18, registers 19-22, blocks of bus drivers 23-29, encoder 30, address decoder 31, clock generator 32, multiplexer 33, R + S triggers 34-36, driver pulses 37. The operation of device 1 is based on the distortion of information (addresses, data) when transmitting it through interfaces in the system under study (computer). The use of the proposed device in an experimental study of reliability allows us to significantly reduce the time of the obtained estimates of the reliability of redundant systems and increase the reliability of the data obtained. 3 il.

Description

The invention relates to computing technology and is intended to simulate failures in an experimental study of the robustness of the functioning of structurally redundant computing systems built using various asynchronous backbone interfaces.

The purpose of the invention is the expansion of the functionality of the device by simulating faults in the cycles of Address and Computer Main Data.

Fig. 1 shows a block diagram of a device for simulating failures and failures, a block diagram of a computer in which malfunctions are simulated, and a computer controlling the proposed device; Fig. 2 shows a fragment of a schematic of a master unit included in a computer in which 1 faults are simulated, and a fragment of a schematic diagram of an external device also included in said computer; FIG. 3 ™ is a time diagram of the device when simulating a fault in the cycle. The address on the mainline of the computer, in which faults are simulated.

In the proposed device, various modes can be implemented to simulate the failures and malfunctions of various devices and units that make up the computer into which they malfunction — setters, external devices, processors, and so on.

In Fig. 1, a device 1 for imitation of failures and failures is indicated, a computer 2 in which faults are simulated, and a computer 3 controlling device I. The computer 2 includes a central processor 4, a setting device 5, external devices,

,20

thirty

25

. ,,

 .

50

55

6 and 7 and RAM 8. Blocks 4–8 are united by a common interface, including control buses 9 and information buses 10, Tires 9 and 10 together form the I & C interface. The IUS interface control buses include 5 groups: addressing control buses (5 buses); exchange control tires (2 tires); tires designed to capture the highway (5 tires); common interface control bus (1 bus); tires for transmitting interrupt signals (8 buses),

The information bus of the I & C interface includes 16 buses over which addresses and data are transmitted. As a computer 2, for example, CM-I634, CM-1210 or another mini- microcomputer can be used, built according to the trunk-modular principle. Modules 4-8 are standard components included in computer 2. Computer 3 is turned on. the central processor 1, the RAM 12, the external device -13, which are combined by the control bus group 14 and the data address bus group 35. As a computer 3 can be used, for example, a computer type of Electronics-60, or a similar type

Device 1 includes memory blocks 16 and 17, control signal encoder 18, registers 19-22, blocks 23-29 of bus drivers, information distortion encoder 30, address decoder 31, clock generator 32, multiplexer 33, RS flip-flops 34-36 and shaper 37 pulses. Position 38 marked the trunk from the output of block 28, connected to the information input of block 16. The encoders 18 and 30 are implemented in the device on the PLA.

515

Figure 2 shows a fragment of the schematic of the setting device 5 and a fragment of the concept of the external device 7 included in the computer 2. The setting unit 5 includes a bus driver unit 39 containing 4 K589AP26 chips connected to the information buses 10, buffer amplifiers 40 (1) - 40 (p) with an open collector and trunk receivers 41 (1) - 41 (p) connected to control buses 9.

The structure of the external device 7 includes a block of 42 mud shapers, buffer amplifiers 43 (1) - 43 (n) and trunk receivers 44 (1) - 44 (n

The operation of device 1 is based on the distortion of information (addresses, data) when transmitting it from one module to another via information buses 10.

The memory block 16 serves to synchronize the time of imitation of malfunctions with the appearance of a specific address (or predetermined and recorded in block 16) transmitted via line 0. At the moment of the appearance of a certain address, the following information appears at the output of block 16:

address of the distortion code in block 17 (3 bits);

the number of the dial that generates the address on line 10 (3 bits);

fault type code (4 bits); failure or malfunction in the address or information part of the trunk cycle.

Block 17 is needed to store the distortion code for each simulated malfunction. For each of the 16 information buses of highway 10 in block 17, two bits are set

type of distortion m (constant 1, constant 0y, inversion of the transmitted bit, no distortion)

The encoder 18 serves to control the operation of the device 1 — to generate control signals for blocks 16 and 17, registers, triggers 34-36, blocks 23, 29, and driver 37. The inputs of the encoder 18 X 1 X. have the following purpose:

X, X fault type code, coming from block 16;

Hu-X-, - trigger values 34-36; Xg signal, acknowledgment

the fact that the address is

0

five

0

X,

X, G

The unit, for which it is required to simulate the malfunction j Xf1 - clock frequencies (see the timing diagrams on

fig.Z);

control signals

IUS interface; X - Addressing Bus

(SPRA);

acknowledgment bus

addresses (ShGSHA);

reset lock bus

sampling (SHBSV);

tire exterior sign

Devices (BWTP);

bus 4 receiver tags

(STD);

data query bus (SHZD); data availability (SND);

bus busy (SHZAN);

X, uh

x, Xf5

X,

Xf7

X, f - tire

x „

X1-tire dump (SHSBR);

five

X1

0

five

device enable signal;

register write control signal 19;

register write control signal 20;

Xt4 recording control signal of block 16;

the control signal recording unit 17;

read register control signal 21. The outputs of the encoder 18 are as follows:

х17х13Х15

Х1Г

Yr

Y31 have

V -

0

Y Y i, i

four

five

41

0

five

Yt

Y Y1o

Ynyn

installation signals in 1 trigger 34-36, respectively; installation signals in O triggers 34-36, respectively; shaper trigger signal 37; respectively, the read and write signals of block 16;

signals to record and disable (transfer to the third state) register 21;

connection signal to transfer the bus driver unit 29; the signal for disconnecting the bus formers of the sensors (blocking the issuance of information

Y., 15

Yu

17

Y -

Y -

Yz, v 121

Y23

15

and control signals in the setters); blocking signal reception control signals in the unit; a signal for disconnecting bus drivers of external devices (6 locking reception and issuance of information and issuing control signals in external devices); blocking signal reception control signals in external devices; signal recording register 19; 20 signal recording register 20;

read signal of block 17;

the trip signal (output switching to the third state) of register 20;

bpoc off signal 23;

turn off register register 19, block 28 register write signal 22;

15646288

A register 22 records the distorted information SoT arriving through block 24 and the encoder 30 from trunk 10.

Blocks 23-29 of bus formers are used to connect the device to the arrays of 9 and 10 computers 2 and buses 14 and 15 t3BM 3. Each block can include several microcircuits of type K589AP16, K559IP2, K559IP1, K589APP26, etc.

thirty

Blocks 24, 27, 25, and 26 are constantly working to transmit information, blocks 23, 28, and 29 are turned on to be transmitted by signals from the encoder 18.

The encoder 30 is required to distort the information word readable from bus 10 (9). For each word of a word read from the interface, there are two bits read from ylock 17 that encode the distortion: 00 - constant 11 - constant 01 - inversion ; 10 - no distortion.

The address decoder 31 serves to organize the recording of registers 19 and 20 and blocks 16 and 17. The clock generator 32 generates three series of non-overlapping clock pulses (Fig. 3). The multiplexer 33 serves to transmit to the encoder 18 a signal that the master for which the malfunction is to be simulated is actually connected to the trunk (it controls the transfer of addresses and data on the trunk at a given time). The input of block 25 receives signals from the Bus Bus that is in each master. The active signal on the bus indicates that this master controls the highway (9, 10) and generates the addresses of external devices. Triggers 34-36 are used to create workflows to simulate faults. Shaper 37 serves to report to computer 3 that a predetermined fault has been entered. The output of the imaging unit 37 is connected to the interrupt bus of the computer 3, and after the completion of the fault simulation, it generates a pulse of a predetermined duration, which informs the computer 3 about the end of the fault simulation.

Y, read signal registers YY YY YYY "YaT

Yl Y "

Y3opa 22;

control signals

IUS interface;

SPRA;

SPPA;

SBSV;

SHPVU;

SPPR;

SHZD; Y3 SND; Yn ShSBR.

Registers 19 and 20 are used to write blocks 16 and 17, respectively. The outputs of register 19 and block 23 have three states (similar to the outputs of registers 20 and 21), so that only one of them works for transmission at one time, the other is turned off,

The register 21 records (records) information from the output of block 16; Three groups of information outputs of the register correspond to three groups of information from the output of block 1

five

d 0

five

thirty

35

40

45

50

55

Blocks 24, 27, 25, and 26 are constantly working to transmit information, blocks 23, 28, and 29 are turned on to be transmitted by signals from the encoder 18.

The encoder 30 is required to distort the information word readable from bus 10 (9). For each word of a word read from the interface, there are two bits read from ylock 17 that encode the distortion: 00 - constant 11 - constant 01 - inversion ; 10 - no distortion.

The address decoder 31 serves to organize the recording of registers 19 and 20 and blocks 16 and 17. The clock generator 32 generates three series of non-overlapping clock pulses (Fig. 3). The multiplexer 33 serves to transmit to the encoder 18 a signal that the master for which the malfunction is to be simulated is actually connected to the trunk (it controls the transfer of addresses and data on the trunk at a given time). The input of block 25 receives signals from the Bus Bus that is in each master. The active signal on the bus indicates that this master controls the highway (9, 10) and generates the addresses of external devices. Triggers 34-36 are used to create workflows to simulate faults. Shaper 37 serves to report to computer 3 that a predetermined fault has been entered. The output of the imaging unit 37 is connected to the interrupt bus of the computer 3, and after the completion of the fault simulation, it generates a pulse of a predetermined duration, which informs the computer 3 about the end of the fault simulation.

The operation of the device is described for one mode - imitation of a failure in the address part of the cycle for the I & C interface

(OST 24.908-80). The proposed device can be used in other interfaces, and the logic of the encoder 18 is changed.

Timing diagrams of the mode are shown in FIG.

Simulation of any malfunction by device 1 is preceded by the setting of this device, as follows:

1. It is determined when the address (or after occurrence) of which address on line 10 is imitated is detected. This address from computer 3 is written to register 19 (block 23 is turned off in the third state).

2. Determine the type of malfunction (failure, failure), the setpoint number 1 on line 10, which must form the address specified in n, 1, after which this fault is assigned a specific number; which simultaneously serves as the address in block 17. The distortion code is stored in block 17 at this address (fault number). The distortion code contains 32 bits (for the 16-bit word on line 10) and sets separately for each of the 16 bits the type of distortion — constants O, 1, inversion, no distortion.

At the address specified in claim 1, and recorded in register 19, the block 28 is recorded in block 16 from computer 3, the information specified in claim 2.

Then, the malfunction number (address for block 17) is recorded into register 20 from computer 3, after which, through block 28 from computer 3, two 16-bit words of the distortion code are recorded in block 17 in two stages. Block 17 has two recording signals (59 and 60) which provide the possibility of such sequential recording with, using the address decoder 31, Signal. readout to block 17 alone, therefore, the 32-bit word is read. At the time when register 20 is working to transmit the address to the input of block 17, register 21 is in the third state. This is ensured by the logic of the operation of the encoder 18. At the initial moment of time after turning on the power in the computer 3, a reset signal Xio is generated, by which triggers 34-36: Y2, Y, - X10 are reset.

The operation of the device 1 when simulating a failure of the type of failure specified in PP.1 and 2, begins after writing to the register 20 1 in the bit that is connected to the input Xt of the encoder 18.

1) Yj0 X - trip signal

register $ 20

-G c signal to turn off register 19, block 28. The output connected to input X41 in register 20 has only two states, all the rest three. Register 20 can be implemented, for example, on K589IR12 and 155TM2 microcircuits.

2) Y21 X2, - unit 23 operates to transmit information from highway 10 to the address input of unit 16.

3) On the bus.10 (the data address bus — SHADOO-SHAD15) the address defined in item 1 (FIG. 3) appears.

4) Signal of address sign X 17 1 appears on the ADD bus (X 2). This signal does not pass to the device (one of 6-8) connected to trunk 10 as the signal is on

Y 1, blocking NOD in devices. Thus, the addressing operation of the selected (one of 6-8) devices is not

5) Y, (XMX, -Xq + XMX

SP 11

9 LPL g1x 10) X6

reading block 16;

Yt Х1гХг, Х9 installation in the trigger 34 (Xs) t

6) Y,.,, X 10 Xfi - register register 21 - on the leading edge Y f1, After recording register 21, code 0101 appears at the inputs X., - X4, in which it is set that the fault X1 0 is simulated, failure X g i

in the address part, the X + lj cycle cycle at the address input of block 17 appears the address where it stores information about the types of distortion in the address for each of the 16 bits; at the address input of the multiplexer 33 there will be the number of the reference, which should form this address.

7) At the input of Xg, 1 appears in that section, if the address has generated a pre-defined in clause 2.

8) Yig XrX7-Xg-X X5 (XJ - reading block 17;

Y3 X -Xj-X - setting to

T

eleven

trigger 35 (X6)

9) Y2 .Xg -record in the register 22 of the distorted address - on the leading edge of the signal Y7 ,,

YU)

 g

 X i X s X 1

a record

block 16 (since a one-fold failure is simulated).

11) Y5) 0- setting trigger 36.

12) Y13 X7 - blocking the issuance of the address and signal of the ADN in the setters (Fig. 2);

Y, (-, reset the blocking signal of the IDMS in the receiver devices (6-8).

13) Yt4 X7

read out register 2.2 (or a corrupted address in trunk 10).

14) YT XyXj- reset trigger

X11 + X7 XS + Y1SH, 34,

15) Y45 X7 X giving signal to the SPRA,

5th, e (X

YU

+ X, „) - video

(,

X7 X1} -X5-Y Reset Trigger Reset Trigger

16) Y, Hera 35.

17) Y 36.

Thus, the simulation of a malfunction of the type of failure in the mobile part of the computer trunk cycle ends.

Depending on what value the X8 signal received after setting in 1 trigger 34 (see clause 7), and also depending on the code recorded on register 21 after setting -in 1 trigger 34, then three types of operations can be performed :

1) a failure simulation (if the corresponding code X g 0 is recorded on register 21);

2) a simulated failure, which differs from a failure simulation in that the information is erased in block 16 at the address specified in c. Claim 1 thus provides one. the multiplicity of its action;

3) resolution of the normal operation of the computer 2 - should be the blocking of the ADG signal (Y) for the time required to fix the address in one of the addressed devices (6-8).

The imitation of rollback differs from the imitation of a crash only in that there is no signal Ys (Fig. 3), i.e. In block 16, the information on the faulty tee is not erased.

The resolution of the normal operation of the computer 2 is as follows.

If the address on line 10 did not coincide with the one specified in Clause 1 or coincided, but was formed by the wrong unit (specified in Clause 2), that is, signal X. 0, then blocking is cleared

0

five

0

0

five

.five

0

five

0

five

CW signal Yi: Y

Xi Xj X

x5x

+ x, x.

1Ј 5 8 5

+ Xj-x,. When the CRW signal is removed, which automatically follows after addressing the selected (one of 6-8) devices, the CRW lock signal is set again. This is done by resetting trigger 34 by setting to

  + x, hg.he-x4 + x, .x

X3-X4).

Thus, the resolution of the normal operation of the computer 2 is ensured.

In the proposed device can be implemented and other modes of operation, such as a failure in the information part, a failure in the address part, and others.

Claims (1)

The use of the proposed device in an experimental study of reliability allows us to significantly reduce the time required for obtaining estimates of n4 & Rage of redundant computing systems and to increase the reliability of the data obtained. Invention Formula A device for simulating computer failures and failures, containing the first and second memory blocks, the first and second registers, the trigger, the first, second and third blocks of bus drivers, the first information inputs of the first and second blocks of bus drivers connected to the input of the device for connecting to the bus addresses of the data of the computer under investigation, the second information inputs of the first and second blocks of bus drivers are connected to the input of the device for connection to the control bus of the computer under investigation, the output of the first block of bus driver It is connected to the input of the address of the first memory block, which is so that, in order to expand its functionality by simulating failures and failures in the Address and Details of computer mainframes, it contains the third and fourth registers, from the fourth the seventh blocks of bus drivers, address decoder, second and third triggers, pulse driver, multiplexer, clock generator, control encoder, information distortion encoder, the output of the third bus driver block connected to output inputs of the first and second memory blocks, the output of the first 13 the memory unit is connected to the information input of the first register, the first output of which bits is connected to the information input of the fourth block of bus drivers and the address input of the second memory block, the second output of the bits of the first register is connected to the address input of the multiplexer, whose information input is connected to the output of the fifth block of bus drivers, the third output of the bits of the first register is connected to the first to fourth inputs of the control encoder, the first and second outputs of which are connected respectively with the S and R inputs of the first trigger, the third and fourth outputs of the control encoder 156 connected to the S- and R-BXO-s of the second trigger, respectively; the fifth and sixth outputs of the control signal encoder are connected to the S- and R-inputs of the third trigger, respectively, n . ABOUT 462814 the second write inputs of the second memory block, the thirteenth to the sixteenth outputs of the control signal encoder form the device lock output, the outputs of the seventeenth to twenty-second control signal encoder are connected respectively to the write inputs of the third and second read registers of the second memory block, translation control outputs in the third state of the second and third registers and control of the first and third blocks of bus drivers, the twenty-third and twenty-fourth outputs of the control signal encoder als are respectively connected to the read and write inputs of the fourth register having an information input coupled to an output of the encoder distortion information, the first input coupled to an output of the second memory unit, the second input of the encoder coupled to the distortion information vyho15 20 the sixth, seventh, and seventh entrances of the encoder is the 25th house of the second busbar block The control signals are connected to the outputs of the first, second, and third triggers, respectively; the seventh output of the control signal encoder is connected to the input of the pulse former; the eighth through twelfth outputs of the control encoder are connected to the write and read inputs of the first memory block, write, and transferring the outputs to the third state of the first register and controlling the fourth block of bus drivers, the multiplexer output is connected to the eighth input of the control signal encoder, from the ninth to the eleventh inputs of which are connected respectively to the first, second and third outputs of the clock pulse generator, the information input of the sixth block of bus drivers is connected to the input of the device for connection to the control bus of the computer under investigation, the twelfth to the twentieth inputs of the control encoder are connected to the output of the sixth block of bus drivers , the output of the first bit of the second register is connected to the twenty-first input of the control signal encoder, from the twenty-second to the twenty-sixth inputs of which of the respectively connected first to fifth outputs of the address decoder, the sixth and seventh outputs are connected to the first and 0 five 0 five 0 five the information inputs of the second and third registers and the address decoder and the input of the third block of bus drivers are connected to the input of the device for connection to the control computer information bus, the outputs of the third and second registers are connected to the address inputs of the first and second memory blocks, output of the fourth block bus drivers are connected to the output of the device for connecting to the information bus of the control computer, the control input of the address decoder is connected to the input of the device for connecting to the control computer control bus, the output of the pulse generator is the output of the device for connection to the control computer control bus, the output of the fourth register is connected to the output of the device for connection to the data address bus of the computer under investigation, the outputs from twenty fifth to thirty second control coders signals are connected to the information input of the seventh bus driver unit, the output of which is connected to the output of the device for connection to the control bus of the EEM under study, the information input of the fifth busbar unit Formed drivers are formed by the device inputs for connecting to the outputs of the occupancy of devices of the computer under investigation.