SU1179325A1 - Random number sequence generator - Google Patents

Abstract

A GENERATOR OF RANDOM NUMBERS SEQUENCES, containing a random number sensor, a memory block, a first key, the output of which is connected to the installation inputs of the first and second counters, the outputs of which are connected respectively to the information inputs of the second and third keys, the outputs of which are connected respectively to the first and second inputs of the block elements OR, the output of which is connected to the first input of the comparison circuit, the control unit, characterized in that, in order to simplify the generator, it contains two delay elements and three s counter and the control unit comprises six AND gates, two trigger and clock pulse generator, whose output is connected to first inputs of first and second AND gates, whose second inputs are connected respectively to the forward and .inversnomu outputs of the first flip-flop. the direct input of which is combined with the inverse input of the second flip-flop and connected to the overflow output of the third counter, the information output of which is connected to the address input of the memory unit, the information input of which is connected to the output of the random number sensor, and the output of the memory block and with the information input of the first key, the output of which is the generator output, the output of the comparison circuit is connected to the control key of the primary key, to the direct input of the second trigger and to the input of the first key. element (L ta delay, the output of which is connected to the input Poll random number sensor and the input of the second delay element, the output of which is connected to the installation input of the third counter, the counting input of which is connected to the output of the first element s | And with the first inputs of the third and fourth And elements, the outputs of which are connected respectively with upN9 equal inputs of the second and third keys, the output of the second element AND SL is connected to the inverse input of the first trigger and with the first inputs of the fifth and sixth elements And, the cat outputs The connectors are connected to the counting inputs of the first and second counters, respectively, the direct output of the second trigger is connected to the second inputs of the third and fifth elements, and the inverse output of the second trigger is connected to the second inputs of the fourth and sixth elements I.

Description

The invention relates to computing and can be used as a set-top box or internal unit of an electronic computer.

The aim of the invention is to simplify the generator and increase its speed.

The drawing shows the block diagram of the proposed generator.

The generator contains a counter 1, a block 2, a 3-comparison circuit, a key 4, counters 5 and 6, keys 7 and 8, a block 9 of elements ШШ, a delay element 10, a sensor -11 random numbers delay element 12 and a control block 13, which contains a generator 14 clock and fflylkov, elements And 15-20, triggers 21 and 22..

Sequence generator random numbers works as follows.

In the initial position, the counter 1 is set to zero. Memories 2 and counters 5 and 6 contain independent implementations of a random variable distributed according to the required law generated by a sensor of 11 random numbers. In this case, in block 2 of the memory there are n numbers, and in counters 5 and 6 the same number. At the output of the comparison circuit 3, there is no signal, therefore, the key 4 is locked and the number is not output at the devices. The trigger 21 opens the element And 15 and closes the element And 16. The trigger 22 opens the elements And 17 and 19 and closes the elements And 18 and 20. There are no signals on all tires.

The impulse from the generator 14 clock pulses through the element And 15 enters the pin Sh1 and through the elements And 1 5 and 1 7 on the bus Sh2. On the bus. P1 signal is transmitted to the counting input of counter 1. Via bus P2, the signal arrives at the enable input of key 7. Counter 1 sets the next value of the address of memory block 2, which is fed to the address input of memory block 2. At the output of memory block 2, a number written at the address set by 1 is displayed. This number is transmitted to the first information input of the comparison circuit 3 and to the information input of the key 4.

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The second information input of the comparison circuit 3 via the key 7 and the block OR 9 receives the number recorded earlier in the counter 5. At the output of the comparison circuit 3, a signal appears if a comparison has occurred, otherwise the signal is not produced. If the signal does not appear, key 4 remains locked and the number from memory block 2 does not arrive at the output of the random number generator. The device works in a similar way until then. Until a comparison signal appears at the output of the comparison circuit 3, or the counter 1 does not overflow.

Let the overflow of the counter 1 occur, i.e. A sequential comparison of the contents of counter 5 with all n numbers stored in memory block 2 was carried out. Counter 1 is transferred to its original. State. At the output of the overflow 25 of the counter 1, a signal appears which, via bus 6, enters the counting inputs of the flip-flops 21 and 22, changing their states to opposite ones. In this case, the elements And 15-19

30 closes and elements 16, 18 and 20 open.

The next impulse from the generator of 14 clock ig-pulses through the elements And 16 and 20 goes to the ShZ bus,

JJ through the element AND 16 - to the installation input of the trigger 21, set it to its original state, which leads to the opening of the element 15 and the closing of the element 16. The signal

0 through the SHZ bus is transmitted to the counting input of counter 6, reducing its content by one.

The next pulse from the generator is 14 clock pulses.

45 through the element And 15 on the bus Ш1 and through the elements And 15 and 18 - on the bus Ш4. From the bus Ш1 the signal is transmitted to the counting input of the counter 1. On the bus Ш4 the signal goes to the enabling

50 key entry 8. In counter 1, the next value of the address is set, which, getting to the address input of memory block 2, causes the arrival of the number written by this

55 address from the memory unit to the first information input of the comparison circuit 3 and to the information input of the key 4. To the second information input

3

The comparison circuit 3 through the key 8 and the block OR 9 enters the contents of the counter 6. In the case of coincidence of the numbers supplied to the inputs of the comparison circuit 3, a signal appears at its output. Otherwise, the device repeats the comparison cycle.

If the comparison of all numbers from memory block 2 with the contents of counter 6 does not occur, then the output of the overflow of counter 1 is the signal that arrives at the bus Ш6. From the bus 6, this signal is transmitted to the counting inputs of the flip-flops 21 and 22, changing their states to opposite ones. At the same time, elements 16 and 17 and 19 are opened and elements 15 and 18 and 20 are closed. Another pulse from the generator 14 clock pulses through the elements Both 16 and 19 enter the bus Sh5, through the element 16 and to the installation input of the trigger 21, reset it, which leads to the opening of the element 15 and the closing of the element 16. The signal through the bus 5 passes to the counting input of the counter 5 by increasing its content by one. Further, the operation of the device continues for

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of the described scheme until the comparison of the number from memory block 2 with the contents of one of the counters 5 or 6. At the 5 output of the comparison circuit 3, a comparison signal appears that opens the key 4 and enters the input of the delay element 10 . A number from memory block 2 whose address is set to

to counter 1, through key 4 enters the output of the device, as well as the installation inputs of counters 5 and 6, and is written to them. From the output of the element 10, the delay signal arrives

5 to the input of the sensor of random numbers 11 and to the input of the element 12 delay. The random number sensor 11 generates the next number that is recorded in place of the number received at the output of the device, since the value of the address in counter 1 has not changed. From the output of the delay element 12, the signal is transmitted to the input. Setting the counter 1 to zero and sets it to the zero state (the state corresponding to the starting address of the memory block 2). The device is reset. The work cycle of the random number generator ends.

Output

Claims (1)

RANDOM SEQUENCE GENERATOR, comprising a random number sensor, a memory unit, a first key, the output of which is connected to the installation inputs of the first and second counters, the outputs of which are connected respectively to the information inputs of the second and third keys, the outputs of which are connected respectively to the first and second inputs of the element block OR, the output of which is connected to the first input of the comparison circuit, a control unit, characterized in that, in order to simplify the generator, it holds two delay elements and a third counter, and the control unit contains six AND elements, two triggers and a clock pulse generator, the output of which is connected to the first inputs of the first and second elements AND, the second inputs of which are connected respectively to the direct and inverse outputs of the first trigger, direct input which is combined with the inverse input of the second trigger and connected to the overflow output of the third counter, the information output of which is connected to the address input of the memory unit, the information input of which is connected to the output of the random number sensor, and the output of the memory block is connected to the second input of the comparison circuit and to the information input of the first key, the output of which is the output of the generator, the output of the comparison circuit is connected to the control input of the first key, with the direct input of the second trigger and with the input of the first delay element the output of which is connected to the Poll sensor input and the input of the second delay element, the output of which is connected to the installation input of the third counter, the counting input of which is connected to the output of the first element And with the first inputs of the third and fourth elements AND, the outputs of which are connected respectively to the control inputs of the second and third keys, the output of the second element And is connected to the inverse input of the first trigger and to the first inputs of the fifth and sixth elements AND, the outputs of which are connected to the counting the inputs of the first and second counters, respectively, the direct output of the second trigger is connected to the second inputs of the third and fifth elements And the inverse output of the second trigger is connected to the second inputs of the fourth and sixth elements I.