SU1413638A1 - Device for interfacing peripherals with trunk line - Google Patents

Abstract

The invention relates to computer technology and can be used to interface external devices with a highway, in particular, for interfacing digital measuring devices with an instrument interface highway. The aim of the invention is to reduce the hardware cost of the device. The goal is achieved by the fact that the device containing the address register, three single vibration dampers, two flip-flops and the NL-HES element, have three AND elements, a counter and an address comparator. 2 Il. g (L with:

Description

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And it relates to computing technology and can be used to interface external devices with a highway, in particular for interface of digital measuring devices with a device interface bus.

The purpose of the invention is to reduce the hardware cost of the device.

Fig, 1 shows a functional diagram of the proposed device; in fig. 2 - the algorithm of the device operation, (asterisks indicate operations performed by the interface controller, other operations are performed by the proposed device).

The device contains a register of 1 address, one-shot 2-4, the elements And 5 and 6, the counter 7, the triggers 8 and 9, the comparator 10 addresses, the element OR NOT 1 1 and the element 12.

FIG. 1 shows 13 data bus lines, reset 14 bus, 15 bus gate bus 15, bus receive readiness bus 16, bus 17 bus / Received data, bus pin 18 Transmission end, control bus 19, input 20 of external device recording (WU) and input 21 readings of the control unit.

A feature of the proposed device is the interpretation of odd bytes as an address, and even ones as data.

The device implements the following interface functions: Initial installation (WELL procedure), Instrumentation message (PS procedure), Parallel polling (software procedure).

According to the NU procedure, the proposed device is reset, and a pulse is formed on the bus 14. When performing the PS procedure, the device operates in the mode of data recording in the VU. The software procedure provides for the device to operate in the data reading mode of the slave. When the PS procedure is performed. Following data translation on bus 13 on bus 15, a low level is established, the contents of counter 7 (output code) are incremented, and if the contents become odd, then a high level is generated at the synchronization of address 1. resulting in a register of 1 address fikspv t byte address.

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The coincidence of the m bits of the register 1 address with the code set on the m terminals of the primary address results in a low level setting at the output of the comparator 10 address. After that, the trigger 8 goes to the zero state, then at the output of the trigger 8, a high level arrives at the bus 17.

If several proposed devices are connected to the trunk, then only one of them (addressed to the exchange) forms a low level on bus 16, the others retain a high-impedance state.

The interface controller, receiving the bus 17 transition signal to the high level state, returns the bus 15 to the high level state, after which the one-shot 4 generates a pulse that sets the initial low level on the direct output of the trigger 9 and on the bus 17 and then the trigger 8 output is set to a high impedance state leading to the formation of an initial high level on bus 16.

This completes the exchange of signals on the sync bus (bus 15-17) between the interface controller and the proposed device via the trunk when receiving a data byte.

Until the next odd data byte arrives, the output code of address register 1 containing the primary and secondary addresses is unchanged.

When receiving even bytes, also. followed by pin 15, the output code of the 7 byte counter becomes even. The parity attribute is allocated by the decoder, implemented on elements 11 and 12. At the same time, element 6 generates a signal Record to input 20 of the control unit. On a positive edge, mounted on buses 13 and outputs of register 1, this signal is recorded in the slave register, which is addressed to receive via bus A1 ... A (8th) secondary address.

The exchange of signals on pshnam 15-17 is the same as when receiving odd bytes (address for the device).

The controller translates the last byte interface controller with a low level on bus 18. At the end of the reception of the last byte on bus 18, the controller sets again

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a high level, in which the one-off oscillator 2 resets the counter 7. After that, the device is reset,

When performing the software procedure, the device can work not only in the read mode, but also in the information recording mode into the device if there is more than one byte of data in the controller message, and the record is made even bytes by the addresses set by previous odd bytes .

A read signal at the input 21 of the slave is formed after the last byte has been transmitted at the moment of signal exchange on buses 18 and 19 in accordance with the algorithm.

On the positive edge of the read signal, the tires 13 are set to the data of the addressed source. Thereafter, after a time determined by the controller, the initial high level is established on tires 18 and 19.

When using multiple source bytes, the software procedure must be turned on for each address.

Claims (1)

Invention Formula A device for interfacing external devices with a trunk containing an address register, three single-oscillators, two triggers and an OR-NOT element, the information inputs of the address register being the inputs of the device for connecting the main bus and an external device to the data bus; The input of the device for connection to the bus. The end of the transmission line, the output of the first trigger is connected to the input of the second one-shot and is the output of the device for connection to the bus. Ready reception (-1 line, input one third) first monostable coupled to a first inverted input of the first flip-flop and is an input device for connection to data bus strobe bus, said first address register group is a group O device outputs for connection to the address inputs of the external device. with five 0 5 0 five . . 0 38 outlets (s / 1 of the second one-shot is connected to the synchronous input of the second flip-flop, the direct output of which is the output of the device for connection to the bus line) Data is received, the inverse output of the second flip-flop is connected to the input of the first flip-flop, the output of the third one-shot is connected to the first one of the second a trigger, the second reset input of which is the input of the device for connection to the trunk reset bus and an external device, characterized in that, in order to reduce the equipment cost, it contains three elements mA, counter, address comparator, the first and second installation inputs of the counter are connected respectively to the second reset input of the second trigger and the output of the first one-vibrator, the second group of outputs of the address register is connected to the first group of inputs of the address comparator, the second group of inputs of which is a group of inputs devices for connecting to the address outputs of an external device, the output of the address comparator is connected to the first inversion-w inputs of the first and second elements AND and the second reset input of the first trigger, all The m fallen digit of the counter is connected to the first inverse input of the third element AND and the synchronous input address register, the outputs of the higher bits of the counter through the element OR NOT are connected to the BTopbLM inverse of the third element And, the inverse output of which is connected to the second inverse of the second element And, the output of which is the output of the device for connecting the external device to the recording input, the synchronous input of the counter is connected to, the input of the third one-shot, the second and third inverse inputs of the first element And are connected At the input of the second one-shot and the input of the device for connection to the bus control bus, the output of the first element I is connected to the third inverse input of the element I and is the output of the device for connection to the reading input of the external device. 146 IFC 15 L, 0UQ.i  Start ° L JIZI -TffpedovQ bytes on) bourn  OI "0 message X Jl EOI 1 throw j cvemvuffu jfO / upooKa records and ( sanucti Record J / 7- / JIPReg code registers SlOlf ei Cfpoc trtgerae NffrS 0 ycrnoffffSfta mpuiie fxi fO 8 oMCff. OQMCHoe condition Jl CSpoc trigger. L J l / sac o Jl. Installation of obaff about obfcoffouffn - comp. f / lff Tjyutte- jifffneoM  I