JPS63231665A - System for effectively using bus - Google Patents

Abstract

PURPOSE:To use a pair of busses as address busses and data busses in time division by providing one bit to discriminate the use of busses. CONSTITUTION:If the output of an output control circuit 8 is set to the high impedance state of three states in case of a discrimination signal 4 is in the high level and the output of a bidirectional output control circuit 9 is set to the high impedance state of three states in case of the discrimination signal 4 is in the low level, address/data busses 5 and 5' are used as data busses when the discrimination signal 4 is in the high level, and they are used as address busses when the discrimination signal 4 is in the low level. Thus, address/data busses are used as address busses or data busses in time division.

Description

[Detailed Description of the Invention] [Summary] In a circuit that requires an address bus and a data bus,
In order to solve the problem of increasing the number of buses, one set of identification bits is provided to identify the purpose of the bus, making it possible to share one set of buses as an address bus and a data bus in a time-sharing manner. It is something.

[Industrial application field]

The present invention relates to a configuration method for an address bus and a data bus. Address buses and data buses are becoming widely used in digital circuits, as well as circuits with microprocessors. In particular, as 16-bit microprocessors have come to be widely used, the proportion of the address bus and data bus in the circuit has tended to increase. For example, an 8-bit microprocessor has 12 address buses and 8 data buses, but a 16-bit microprocessor has 24 address buses and 16 data buses, which doubles the number of buses. The RC of the bus connection also doubles, and the hardware scale of the circuit also increases. Therefore, there is a need for a bus configuration system that can reduce the hardware scale of the circuit and reduce the cost.

[Conventional technology]

FIG. 3 shows an example of the configuration of a conventional address bus and data bus. In the figure, 1, 1", 1" are address buses, 2.2',
2' is a data bus (bidirectional), 3.3", 3" is a control signal bus, 11.13 is a bus driver, 14,
16 is a bus receiver, 12.15 is a bidirectional bus driver/receiver, 17 is an address decoder, 18 is a decoder output, and 11 to 17 are each composed of an IC. Note that 19 is a control section, and 20 to n are a plurality of controlled sections.

As shown in the figure, in the conventional address bus and data bus configuration system, the address bus and data bus are provided separately and independently, so the number of buses is large, and the number of ICs is also large. It tends to increase.

[Problem that the invention seeks to solve]

In the conventional address bus and data bus configuration method, the address bus and data bus are provided completely separately, so as the capacity (number of signals) of each bus increases, the wiring between the control section and each controlled section increases. A problem has arisen in that the amount of hardware and the amount of hardware for each controlled section also increases significantly.

[Means for solving problems]

FIG. 1 is a diagram showing the principle of the transmission side of the bus effective utilization method of the present invention. In the figure, the output side of the latch circuit 6 and the output control circuit 8 connected to the address bus 1,1°, and the output side of the latch circuit 7 and the bidirectional output control circuit 9 connected to the data bus 2.2°. and address/data bus 5°,
5 to the bus driver/receiver circuit 10 and send it to the receiving side.

The clock signal and write control signal 3 are connected to latch circuits 6 and 7, and the identification signal 4 is connected to output control circuit 8 and bidirectional output control circuit 9 via inverting circuit 30.

On the receiving side, the configuration is the same as in FIG. 1 except that the directionality of the output control circuit 8 and the direction of the address data signal are reversed.

[Effect]

In FIG. 1, the output control circuit 8 is
By performing three-state control of the gate output of the bidirectional output control circuit 9, it is possible to control whether the bus actually connected between the circuits is used as an address bus or a data bus. . This bus selection selects either the address bus or the data bus, which is connected to the bidirectional bus driver/receiver circuit 10 via the address/data bus 5' and transmitted to the receiving side via the address/data bus 5.

The control method using the surface identification signal 4 uses an IC circuit (for example, 74LS244.245) having a known three-state control function as the output control circuit 8.9, and sends the write control signal 3 synchronized with the clock signal to the latch circuit 6. and enter in 7,
The level of the identification signal 4 is set to "H" or "L".

When the identification signal 4 is at "H" level, the output of the output control circuit 8 is in a three-state high impedance state,
If the output of the bidirectional output control circuit 9 is set to be in a three-state high impedance state when the identification signal 4 is at the "L" level, the address/data dual-purpose bus is set when the identification signal 4 is at the "H" level. 5,5' serves as a data bus, and when the identification signal 4 is at the "L" level, the dual-purpose bus 5.5' serves as an address bus.

As described above, the address/data bus can be used as an address bus or a data bus by time division.

〔Example〕

FIGS. 2(a), 2(b), and 2(c) show a configuration diagram of an address bus and a data bus, a circuit diagram of the transmitting side, and a time chart thereof, according to an embodiment of the present invention.

In the figure, 1.1'' is an address bus, 2.2', 2'' is a data bus, 3.3', 3'' is a control bus, 4゜4'', 4'' is an identification signal, 5.5', 5 ” is the address/
Data bus, 21. 26 is a bus selector circuit, 22
．． 24 is a bidirectional bus driver/receiver, 23 is a bus driver, 25 is a path receiver, 27 is an address decoder, 28 is a bidirectional buffer gate, 29 is a decode output, 19 is a control section, and 20 to n are A plurality of controlled parts.

In FIG. 2(a), the address bus 1 and data bus 2 of the control section 19 are controlled by three-state control of the gate outputs of the latch circuit and output control circuit that constitute the bus selector circuit 21, using the identification signal 4. , either the address bus or the data bus is selected and the address/data bus is selected.
It is placed on the data bus 5゜5゛, 5'' and is connected to the controlled section 20.The path selector circuit 26 of the controlled section also receives the input side address / It operates to select either the address bus or the data bus as the data bus.

In the controlled section, the bidirectional buffer gate 28 is controlled by the decoded output 29 from the address decoder 27. Since there are 20 to n of controlled units, the number of bus drivers/receivers 22 and 24 of the control unit 19 and controlled units 20-n and the number of buses between the controlled unit 19 and controlled units 20 to n are as follows. It can be significantly reduced.

Figure 2 (b) is an example of a circuit diagram when both the address bus and data bus are 8 bits. The IC used is the 7dLS series, but it can be replaced with other ICs with similar functions. be. In the figure, 7 and 7' indicate latch circuits for writing and successive output, and together with 9 and 10, they are composed of IC circuits having a three-state function, and each terminal has the terminal symbol shown in the figure. connected by bus.

FIG. 2(c) shows a time chart for one cycle of write/read in the above circuit diagram, and can be used for both address/data by “H” or “L” of the clock signal, write control signal 3, and identification signal 4. This shows a state in which the bus 5 is used for write addresses, write data, successive addresses, and successive data in a time-sharing manner. The line marked * on the time chart is for three states.

Indicates high impedance state.

〔Effect of the invention〕

According to the present invention, the hardware of the bus driver and bus receiver in the control section and the controlled section and the number of buses between the control section and the controlled section can be significantly reduced, so a highly flexible and inexpensive system can be constructed. There is an effect that can be done.

[Brief explanation of drawings]

Figure 1 is a diagram of the principle of the present invention (transmission side), Figure 2 (a),
(b) and (c) show a configuration diagram, a circuit diagram (transmission side) and its time chart of an embodiment of the present invention, and FIG. 3 shows a configuration diagram of a conventional example. In the figure, ■, 1'', 1'' are address buses, 2.2', 2
” is the data bus, 3, 3°, 3” is the control bus,
4.4", 4# are identification signals, 5.5', 5" are address/data buses, 6, 7 are latch circuits, 8 is an output control circuit, 9 is a bidirectional output control circuit, 10.12゜15
, 22.24 is a bidirectional bus driver/receiver circuit;
11.13.23 is a bus driver, 14.16.25 is a bus receiver, 17.27 is an address decoder, 18.
29 is a decode output, 21.26 is a path selector circuit,
2 shows a bidirectional buffer gate, and 30 shows an inverting circuit. Further, 19 indicates a control section, and 20 to n indicate a plurality of controlled sections.

Claims (1)

[Claims] An inter-device bus wiring method comprising a control section and a plurality of controlled sections, which include a plurality of address buses (1, 1') and a plurality of data buses (2, 2'). By applying the identification signal (4) to the address bus and data bus output control circuits (8, 9), the plurality of address buses (1, 1') and the plurality of data buses (2, 2') An effective bus utilization method characterized by sharing the output side of the bus with multiple address/data buses (5, 5') in a time-sharing manner.