JPS5971526A - Microcomputer system - Google Patents

Abstract

PURPOSE:To prevent an increase of wiring and to eliminate the need for a decoder, by selecting a desired integrated circuit from plural memories or integrated circuits for peripheral control to attain data transfer with a microprocessor. CONSTITUTION:When the microprocessor MPU1 selects a specific LSI among 8 LSIs 5-1-5-8, an LSI selection signal CS is transmitted to all the LSIs 5-1-5-8 through an LSI selecting signal line 8 at first. Then, data including LSI address information, 3-bit corresponding to the information to the address of the objective LSI is transferred to the LSIs 5-1-5-8 through a serial interface data line 3. The LSIs 5-1-5-8 compares the LSI address information transferred from the MPU1 with the address correspondence information to attain further data transfer between the MPU1 and the LSI coincident with the information.

Description

[Detailed description of the invention] The present invention relates to microcomputer systems.

Conventionally, in a microcomputer system that has a microprocessor (hereinafter referred to as MPLI) and an integrated circuit for memory or peripheral control 1 (hereinafter referred to as LSI), the MPU integrates multiple memory LSIs or peripheral control LSIs.
When data is transferred by selecting a specific LSI from among the LSIs, data transfer is performed by marking each LSI and transmitting an LSI selection signal from the MPU through a one-to-one corresponding signal line. Alternatively, a decoder may be provided between the MPU and each LSI to decode the LSI selection signal from the fiMPU and transmit the selection signal to the target LSI for subsequent data transfer. It was getting worse.

FIG. 1 is a block diagram of a first example of a conventional microcomputer.

LSI5-1 for MPUI and memory or peripheral control
5-8, data is transferred through the serial interface data line 3, and control signals necessary for this data transfer are transmitted through the control bus 2. Reference numeral 4 denotes eight lines connecting the MPU and the LSI, which are used to transmit LSI selection signals from the MPU to each LSI.

MPU is the LSI and MPU that transfer data among the wiring 4
By transmitting a 1,8I selection signal (referred to as a C8 signal) to the target LSI through the cable connecting the two, it becomes possible to transfer data with the target LSI after serialization. (C8=nitrogen 1
(The LSI to which # is applied is selected.) Therefore, when there are n LSIs, n wirings for LSI selection are required to connect the MPU and each LSI.

The drawback of the first conventional example is that as the number of memory LSIs and peripheral control LSIs increases, the number of wires for LSI selection signals from the MPU to the LSI increases, resulting in complicated wiring. , the MPU requires the same number of terminals for the wiring as the number of LSIs.

FIG. 2 is a block diagram of a second example of a conventional microcomputer.

Numbers 1, 2, 3 and 5-1 to 5-8 in the figures are the same as in FIG. In order to select the target LSI among the eight LSIs, the MPU transmits the encoded signal to the decoder 7 through three LSI selection signal transmission lines 6, and the decoder 7 decodes the encoded signal. , by transmitting an LSI selection signal to the target LSI.
Data transfer becomes possible between U and the target LSI. L
When there are n SI selection signal transmission lines 6, the decoder
It is possible to distinguish between n LSIs. This selection method eliminates the complicated wiring and L
The problem of increasing the number of MPU terminals required to generate SI selection signals is almost solved, but in the second conventional example, the n-bit information generated by the MPU is converted into an LSI selection signal required to distinguish between 2n LSIs. It has the disadvantage that it requires a dedicated decoder.

The present invention eliminates the above drawbacks, selects a desired integrated circuit from among a plurality of memory or peripheral control integrated circuits, and transfers data between it and a microprocessor without using a decoder or increasing wiring. It provides a microcomputer system that enables the transfer.

The microcomputer system of the present invention is connected to the microprocessor through a control bus, a serial interface data line, and an LSI selection signal transmission signal transmission line, and each unique address correspondence information is set. A plurality of peripheral control integrated circuits or memory integrated circuits, an address correspondence information input terminal provided in each of the integrated circuits for inputting address correspondence information, and the microprocessor transfers LSI address information via a serial interface. A control circuit that determines and controls the timing to transfer normal processing data and the timing to transfer normal processing data, and a control circuit that determines and controls the timing to transfer normal processing data, and a comparison circuit that compares the address correspondence information set on the paper; and when the comparison circuit determines a match, the r,
The microprocessor is configured to include a buffer circuit that enables one data transmission between the V circuit and the microprocessor.

Next, embodiments of the present invention will be described using the drawings.

FIG. 3 is a block diagram of one embodiment of the present invention.

Each LSI 5-1 to 5-8 is provided with an address correspondence information terminal. When there are n address correspondence () map input terminals, it is possible to distinguish between 2n LSIs.

In this embodiment, the number of Sl is 8 to 23. Therefore,
There are three address correspondence information input terminals, CA1 to CA3. '1' as address correspondence information to the input terminals 0 people 1 to CA3 of Soshi and Nirera! Enter the depth level or ground level to classify. Now, check the power supply voltage level of 5■
〃, and the ground level is %o〃. MPU has 8 L
When selecting a specific LSI from among the SIs, first, select all LSIs.
The LSI selection signal C3 (-1) is transmitted to the SI through LSI selection signal wiring #8. Next, data containing 3 bits of LSI address information according to the address correspondence information of the target LSI is sent to the serial interface. It is transferred to each L81 through data line 3. Each LSI
The LSI address information transferred from the LI and the address correspondence information are determined to match by a comparison circuit, and the matched LS
Data transfer between I and MPU is possible from now on. M.P.
After U sets the LSI selection signal CB to %Q/F,
By transferring the LSI address information through the serial interface data line 3, it becomes possible to access other LSIs. L shown in the above example
According to the SI selection method, as in the past, the target LS
It is not necessary to apply C8=%1# as an LSI selection signal to I, and set Cf3=QOp to all LS
Since it is only necessary to apply C8=1tt to I, unlike the first conventional example, the wiring for the LSI selection signal is not complicated, and the 8 (PU terminals) for the LSIJ selection signal are also Furthermore, since a decoder for LSI selection is not required, the disadvantage of the finger in the second conventional example is also eliminated.Also, the LSI terminal provided inside each LSI
The circuits for comparing address information and address correspondence information are all the same circuit, and the address correspondence information @ to be input to the address correspondence information input terminal can be inputted according to the purpose, so that the versatility of the LSI is not lost. If the address correspondence information input terminal is an n terminal, 211 LSIs can be connected with one wire for LSI selection.
It is possible to select.

Next, the LSI selection method will be explained in more detail.

FIG. 4 is a detailed circuit diagram of the glaze circuit selection circuit portion of the embodiment shown in FIG. 3. However, for simplicity, there are two address correspondence information input terminals.

In FIG. 4, 9 is a buffer circuit for transferring data between the serial interface data line and the internal data bus through the input terminal 81 and output terminal SO, and 10 is the LS input to the MPU buffer circuit 9.
A circuit 11 latches 2 bits of address information, and 11 indicates address correspondence information input to address correspondence information input terminals CA1 and CA2, and LSI address information CAI', CA2' output from the LSI address information latch circuit 1o.
A comparison circuit 12 is used to set the output Q to %1 when the input S is sIN, and to reset the output Q to %Q# when the input R is 11. 1. When the inputs S and R are both 0, the output Q (and Q) is an R-8 flip-flop that retains the previous state, gate 14 is an inverter, gates 15 and 16 are a three-way AND circuit, Gate 17 is a two-person AND circuit.

The clock generated by the MPU in order to synchronize the timing of data transfer with MPU1 is referred to as the SCK clock, and the SCK clock is
The CK terminal is powered. Further, the LSI selection signal C8 is inputted from the C8 terminal.

13 counts the SCK clock and generates a signal from C1 in synchronization with the falling edge of the 8th clock.
At the SCK clock counter that outputs 2 and 11,
When the C8 signal power is 0, the output of C2 becomes 0.

FIG. 5 is a timing chart during operation of the integrated circuit selection circuit shown in FIG. 4.

After the MPU changes the cs signal from 0 to 0 to IN at time to, it serially transfers 8-bit data (81 to s8) consisting of 2 bits on the LSI address signal 2 through the sI terminal bit by bit. . The data is latched one pit at a time in the buffer circuit in synchronization with the falling edge of the S'CK clock generated by the MPU. When the 8-pit data is latched in the buffer circuit, the LS
The I address information is latched by the LSI address information latch circuit and transferred to the comparison circuit 11, and a match is determined between the LSI address information and the address correspondence information.If they match, data transfer between the MPU and the MPU is performed thereafter. If they do not match, subsequent data transfer is prohibited.

To explain in more detail, the C8 signal input from the C8 terminal of the LSI is passed through the inverter 14 and the AND circuits 15 and 16.
and input to the clock counter 13 at 80. 8
The clock at 80 which is input from the terminal at 0 is AND circuit 1.
5, SCK clock counter 13 and buffer circuit 9
is input.

SCK clock counter 13 generates a signal at output C1. Also, the output C2 is input to AND circuits 15 and 17, H1AND times! The output of 817 is input to the LSI address information latch circuit W810 as an LSI address information latch timing signal.

Data transferred from the MPU is input to the buffer circuit 9 from the S terminal, and when data is transferred to the MPU, it is output from the buffer circuit 9 through the SO terminal, and the buffer circuit 9 is connected to the internal data bus 18. . The LSI address information 2 pit input to the buffer circuit 9 is L.
The SI address information is input to the latch circuit 10, and is sent to the comparison circuit 1 as LSI address information CAI', CA2'.
1 is input. Address correspondence information is Maiko CA1 and C
A2 is input to the comparator circuit 11, the output of the comparator circuit 1 is input to the AND circuit 16, and the output of the AND circuit 16 is input to the buffer circuit 9. When the output of the AND circuit 16 is 11, data is transferred between the buffer circuit 9 and the serial interface data line in synchronization with the SCK clock, and when the SCK clock counter 13 generates a pulse, data is transferred to and from the internal data bus 18. Data transfer is performed with the buffer circuit 9. When the C8 signal is Qi O〃,
The input R of the S flip-flop 12 to the inverter 14 is %1#, and the input S of the AND circuit 15 is 0.
Therefore, the output Q is %O〃, and the output Q is! 1〃 The output of Tonashi Q is 1 ON, and the output of AND circuit 16 is ant Ol.
becomes. Also, the output C of the SCK clock counter 13
2 outputs x□g by inputting the C8 signal %Q#, so the output of the AND circuit 17 is %0, and no LSI address information latch timing signal is generated. The MPU is at time t in FIG.

After changing the C8 signal from QO〃 to %1〃, SCK
The buffer 7 is connected through the SI terminal in synchronization with the rising edge of the clock.
The most significant bit of the 8 bits of the 9 circuit data is input, and the buffer circuit 9 is input in synchronization with the falling edge of the SCK clock.
latched to. Thereafter, one bit is inputted in the same manner in synchronization with the 8CK clock, and in synchronization with the falling edge of the 870th clock of the 5CK (time t1), 2 bits of LSI address information out of 8 bits of data in the buffer circuit 9 are input to the LSI.
The address information is transferred to the latch circuit 10. Also, at time t1, the output of the SCK counter C21): *1 g
The output from the AND circuit 17 becomes +11, and the output becomes 111. Due to the generation of this LSI address information latch timing signal, the LSI address information transferred from the buffer circuit 9 is transferred to the LSI address information latch circuit 10. Get double punched. 8CK clock counter 13
generates a pulse from output C1 at time t1, but AN
Since the output direction of the D circuit 16 is 10, the buffer circuit 9
Data transfer between the internal data bus 18 and the internal data bus 18 is not performed. ,
After that, the next SCK clock rises #) (time h in Figure 5).
), the AND circuit has 15 digits of power and the output is -1r.
fc t), the R-8 flip-flop becomes the input S, so the output of Q becomes '0', AN
D time P-17 outputs -OI, and input to the LSI address information latch circuit 10 is prohibited.

LS latched by LSI address information latch circuit 1o
I address information @CA1', CA2' is transferred to the comparison circuit 11, and the address correspondence information input terminal CA1. Address correspondence information CAI and CA2 inputted by CA2,
A comparison is made between time t1 and time t2, and if they do not match, 1o is output. Therefore, the output of the AND circuit 16 is oI, and data transfer via the buffer circuit 9 is not performed.

On the other hand, if they match, the comparison circuit 11 outputs the signal 1. At this time, the C8 signal and the output Q of the R-8 flip-flop are in the state of %1, so the 3 of the AND circuit 16
Depending on the human power %IN, the output will be the state of town. Therefore, from now on, when data is input through the MP[J7>, etc. 81 terminals, it is latched one bit at a time in the buffer circuit 9 in synchronization with the falling edge of the sCK clock, and after 8 bits of data are latched, the SCK counter 13 is generated. The data is transferred along the internal data bus 18 in synchronization with the pulses. On the other hand, when outputting 8 bits of data through the SO terminal, niha! The fly-tabus 18 outputs 8 bits of data set in the p-buffer register 9 one bit at a time from the SO terminal in synchronization with the falling edge of the SCK clock.

After the address information is latched between times ti and 12 in FIG. 5, the MPLJ changes the C8 signal again to select another LSI and inputs new address information to each LSI. Since the memory is held, the MPU only needs to transfer the first data after changing the C8 signal as chip address information, and the data f
There is no need to enter L8/air address information in advance in the reverse year.

In the above *Embodiment, the transfer data is 8 bits. However, the present invention is also applicable to the case where data other than 8 bits is serially transferred bit by bit. In addition, in Figure 4, there are two address correspondence information input terminals, but this is because, as mentioned above, 2n LSIs can be selected with n terminals, so the address correspondence is determined from the number of C8 signal lines and the number of LSIs. Determine the number of information input terminals.

As explained in detail above, the present invention allows a desired integrated circuit to be selected from a plurality of integrated circuits without requiring much wiring or an external decoder. The effect is significant because it provides a microcomputer system that enables data transfer between computers.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a first example of a conventional microcomputer, FIG. 2 is a block diagram of a second example of a conventional microcomputer, FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. The figure is a detailed review of a portion of an integrated circuit that is not shown in FIG. 3, but is an example of an integrated circuit, and FIG. 5 is a timing diagram during operation of the quadrature circuit selection circuit shown in FIG. 4. 1...MPU (microprocessor), 2...
...Control bus, 3...Data line for serial interface, 4.・・・・・・LS
I selection signal transmission approx. 5-1 to 5-8... LSI
, 6...I, f9I9n signal transmission line, 7...
...Decoder, f3, ...,,,T, 8 I selection signal transmission @gent, 9...Buffer circuit, 10...
...LSI address information latch circuit, 11...
・Comparison circuit, 12...R-S flip-flop, 13...SCK clock counter, 14.
...Inverter, 15,16°17...
AND circuit, 18...internal data bus.

Claims (1)

[Claims] A plurality of peripheral control integrated circuits or memory integrated circuits connected to the microprocessor through LSI selection signal transmission lines, a control bus, and a serial interface data line, each having unique address correspondence information. a circuit, an address correspondence input terminal provided in each of the integrated circuits for inputting address correspondence information, a timing at which the microprocessor transfers LSI address information via a serial interface, and a timing at which normal processing data is transferred; and a comparison circuit that compares LSI address information output from the microprocessor and address correspondence information set to the address correspondence information input terminal under the control of the control circuit. , a buffer circuit that receives the match determination signal when the comparison circuit determines the match and enables data transfer between the integrated circuit and the microprocessor. system.