JPH02311942A - Cpu external access bus system - Google Patents

Abstract

PURPOSE:To decrease the number of interface lines set between a CPU mounting part and a part to receive an access without reducing the capacity of an access space by multiplexing both address and data buses. CONSTITUTION:When an address is transferred to a part 200 to receive an access, a CPU 101 makes the multiplex bus sequence control information show an address cycle and sends an address to the part 200 via a multiplex bus 4. When the data are written, the CPU 101 makes the multiplex bus sequence control information show a data writing cycle and sends the write data to the part 200 via the bus 4. Then the part 200 transfers the data to a CPU mounting part 100 via the bus 4 since the read timing is instructed when the multiplex bus sequence control information shows a data reading cycle. As a result, the number of interface lines can be decreased even if the address space of the part 200 is large.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a CPU external access bus system that can reduce the number of interface lines between a CPU mounting section and an accessed section. .

[Conventional technology]

In a device where a CPU mounting section equipped with a CPU and an accessed section are not located on the same package, conventionally, when connecting the two, the address bus, data bus, and read/write control signal lines are used as they are to connect them. Alternatively, an address decode section that decodes a part of the address output from the CPU and generates a chip select signal is provided in the CPU mounting section, and a chip select signal line that transmits the chip select signal generated by the address decode section is provided. , C
Connection is made using an address bus that transmits the portion of the address output from the PU that has not been decoded by the address decoding section, a data bus, and a read/write control signal line. [Problems to be Solved by the Invention] Among the conventional methods described above, the former has a problem in that the number of interface lines between the CPU mounting section and the accessed section increases, which tends to cause a pin neck. In addition, in the latter case, if the access space of the accessed part is small, the number of interface lines can be reduced compared to the former, but if the access space is large, the number of interface lines can be reduced compared to the former, which uses the address bus as is. There is a problem that the number of interface lines increases.

An object of the present invention is to reduce the number of interface lines even when the address space of the accessed section is large.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a system including a CPU mounting part mounting a CPU and an accessed part accessed by the CPU mounting part, the CPU mounting part and the accessed part being accessed by the CPU mounting part. multiplexed bus,
Connected by a multiplexed bus read line, a multiplexed bus write line, and a multiplexed bus sequence control line, the CPU transfers data to the accessed unit via the multiplexed bus to the multiplexed data output port during an address cycle. The address is set, and information indicating an address cycle is set in the multiplexed bus control signal output port as multiplexed bus sequence control information to be transferred to the accessed section via the multiplexed bus sequence control line. Instructing write timing to the accessed unit via a multiplexed bus write line, and setting data to be transferred to the accessed unit via the multiplexed bus in the multiplexed data output port during a data write cycle; Information indicating a data write cycle is set in the multiplexed bus control signal output port as multiplexed bus sequence control information to be transferred to the accessed unit via the multiplexed bus sequence control line, and then the multiplexed bus Multiplexing that instructs write timing to the accessed section via a write line, and transfers the signal to the multiplexed bus control signal output port to the accessed section via the multiplexed bus sequence control line during a data read cycle. After setting information indicating a data read cycle as bus sequence control information, a read timing is instructed to the accessed section via the multiplexed bus lead line, and the accessed section reads the multiplexed bus sequence control line. When the multiplexed bus sequence control information applied via the multiplexed bus indicates an address cycle, a write timing is instructed via the multiplexed bus write line, thereby causing the address applied via the multiplexed bus to be sent to the address latch section. and when the multiplexed bus sequence control information indicates a data write cycle, write timing is instructed through the multiplexed bus write line, and data added via the multiplexed bus is latched to the address latch. When the multiplexed bus sequence control information indicates a data read cycle, read timing is instructed via the multiplexed bus lead line, and the address is latched in the address latch section. The data at the address is transferred to the CPU mounting section via the multiplexed bus.

[For production]

When the CPU transfers an address to the accessed unit, the CPU sets the multiplexed bus sequence control information n to indicate the address cycle, and transfers the address to the accessed unit via the multiplexed bus.When writing data, the CPU uses multiplexed bus sequence control information n to indicate the address cycle. The write data is transferred to the accessed section via the multiplexed bus with bus sequence control information indicating a data write cycle. Therefore, the accessed section can determine whether an address or write data is being added based on the multiplexed bus sequence control information. Further, when reading data, the CPU transfers the address in the same manner as described above, sets the multiplexed bus sequence control information to indicate a data read cycle, and then instructs the read timing. When the multiplexed bus sequence control information indicates a data read cycle, the accessed unit transfers data to the CPU mounting unit via the multiplexed bus in response to a read timing instruction.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the invention, showing multiplexed bus leads 1. Multiplexed bus light line 2. .

It consists of a CPU mounting section 100 and an accessed section 200 connected by a multiplexed bus sequence control line 3 and a multiplexed bus 4. The CPU mounting section 100 includes a CPU I O1, a decoder 102, a multiplexed bus control signal output port 103, a multiplexed data output port 104, a multiplexed data input port 105, an external interface driver 106, and an external interface dual port. a direction buffer 107, an address bus 111,
Data bus 112 and write control signal line 113
The accessed section 200 includes a multiplexed bus control signal reception buffer 201, a multiplexed bus separation/control section 202, a multiplexed bus bidirectional buffer 203, and an upper address latch section 204. and a lower address latch section 205.

The decoder 102 decodes the address on the address bus 111 and generates a control boat select signal 115 for selecting the multiplexed bus control signal output port 103 or a data boat select signal for selecting the multiplexed data output port 104 or the multiplexed data input port 105. 116. The multiplexed bus control signal output port 103 includes a 1-bit multiplexed bus read bit section b1 corresponding to the multiplexed bus lead line 117 and a 1-bit multiplexed bus write bit section corresponding to the multiplexed bus write line 118. b2, and a 2-bit multiplexed bus sequence control bit part b3 corresponding to the multiplexed bus sequence control line 119 and in which multiplexed bus sequence control information is set, and to which the control boat select signal 115 is applied. In addition, by outputting write No. 13 to the write control signal line 113, data corresponding to each of the bit portions b1 to b3 on the data bus 112 is set. Note that the multiplexed bus sequence control bit part b3 contains information indicating a lower address cycle as a multiplexed bus sequence control signal (in this embodiment, "0"
”, “0”), information indicating the upper address cycle (“0”).

"1"), information indicating the data write cycle ("
1", '0") and information indicating the data read cycle (
"1", "1") is set.

The multiplexed data output port 104 latches data on the data bus 112 by applying data boat select signals 1 and 16 and outputting a write signal to the write control signal line 113. A multiplexed data input capacitor 105 is a bidirectional buffer 10 for external interface at the time when the multiplexed bus read signal on the multiplexed bus lead line 117 changes from "1" to "0".
7, and outputs the latched data to the data bus 112 by being selected by the decoder 102 and outputting a read signal to the read control signal line 114.

The multiplexed bus separation control unit 202 connects the multiplexed bus lead wire 21
1. Read signal 2 according to the states of the multiplexed bus write wA212 and the multiplexed bus sequence control line 213.
15. Light signal 216. Upper address rough clock 217. Lower address latch blocker 218. It outputs a direction control signal 219.

Next, the operation of this embodiment will be explained. First, the operation when the CPU 101 executes a write operation on the address space in the accessed section 200 will be described.

First, 'CPUl0I outputs the address for selecting the multiplexed data output port 104 to the address bus 111, outputs the lower address of the address for executing the write operation to the data bus 112, and outputs the write control signal 41111.
Outputs a write signal to 3.

The decoder 102 outputs a data port select signal 116 when an address for selecting the multiplexed data output port 104 is output to the address bus 111. This data port select signal 116 is output, and a write signal is output to the write control signal line 113, so that the lower address of the address at which the write operation is executed is set in the multiplexed data output boat 104.

Next, the CPULOI outputs an address for selecting the multiplexed bus control signal ratio capo 103 to the address bus 111, and outputs an address for selecting the multiplexed bus control signal output port 103 to the data bus 112.
l. The multiplexed bus write focus section b2 is set to 'Ow, and the multiplexed bus sequence control bit section b3 is set to information indicating that it is a lower address cycle ("0").

The write control signal line 113 outputs data for setting the write control signal line 113 (“0”), and outputs a write signal to the write control signal line 113. The decoder 102 receives a control port select signal 115 by outputting a signal selecting the multiplexed bus control signal output port 103 to the address bus 111.
Output. This control boat select signal 11
5 is output, and a write signal is output to the write control signal *113, so that the multiplexed bus read focus section b of the multiplexed bus control signal output port 103
1. "0" is set in the multiplexed bus write bit section b2, and "0", 0" is set in the multiplexed bus sequence control bit section b3.

Next, CP[Jlol performs processing to change only the multiplexed bus write bit part b2 of the multiplexed bus control signal output port 103 from "0" to "1" and then return it to "0".

The contents of the multiplexed bus read bit part b1 of the multiplexed bus control signal output port 103 are the multiplexed bus lead line 1.
17. External interface driver 106. Multiplexed bus read wAl, multiplexed bus control signal reception buffer 201. - The contents of the multiplexed bus write bit section b2 are added to the multiplexed bus separation control unit 202 via the multiplexed bus lead line 211, and the contents of the multiplexed bus write bit section b2 are sent to the multiplexed bus write line 118. External interface driver 106. Multiplexed bus light line 2. multiplexed bus control signal reception buffer 201;
The contents of the multiplexed bus sequence control focus section b3 are added to the multiplexed bus separation control section 202 via the multiplexed bus sequence control line 212, and the contents of the multiplexed bus sequence control section b3 are sent to the multiplexed bus sequence control line 119. External interface driver 106.
Multiplexed bus sequence control line 3. Multiplexed bus control signal reception buffer 201. It is applied to the multiplexed bus separation control section 202 via the multiplexed bus sequence control line 213.

Furthermore, the lower address set in the multiplexed data output port 104 is determined when the signal on the multiplexed bus write &1118 becomes "L" and the transmission direction of the external interface bidirectional buffer 107 becomes the output side. , bidirectional buffer 107 for external interface. Multiplexed bus 4
The bus is added to the multiplexed bus bidirectional buffer 203 in the child habit 1 section 200 via the bus.

The multiplexed bus separation control section 202 in the child habit 1 section 200 determines that the content of the multiplexed bus write bit section b2 in the multiplexed bus control signal output port 103 applied via the multiplexed bus write wA212 becomes "lo". When the multiplexed bus sequence control bit aBb applied via the multiplexed bus sequence control line 213
If the content force of 3 is "0", '0°, that is, it is a lower address cycle, the lower address latch unit 20
The lower address rough clock 218 is output to the multiplexed bus bidirectional buffer 203, and the direction control signal 219 applied to the multiplexed bus bidirectional buffer 203 is set to "0".
If the transmission direction of 03 is set to the input direction and the contents of the multiplexed bus sequence control bit part b3 are "0", "1°", that is, indicating the upper address cycle, the upper address latch part 204 is set to the upper address latch. The clock 217 is output, and the direction control signal 219 is set to 0'' to set the transmission direction of the multiplexed bus bidirectional buffer 203 to the input direction. Additionally, the multiplexed bus control signal output port 10 is applied via the multiplexed bus write line 212.
When the contents of the multiplexed bus write focus section b2 of 3 becomes “lo,” the multiplexed bus sequence control &1I21
If the contents of the multiplexed bus sequence control bit part b3 applied via the multiplexed bus sequence control bit part b3 is "lo,""O", that is, indicates a data write cycle, the direction control signal 219 is set to "0°" and the multiplexed bus bidirectional buffer Set the transmission direction of 203 to the input direction and output the write signal 216,
When the content of the multiplexed bus read bit section b1 added via the multiplexed bus read &j1211 becomes '1',
If the contents of the multiplexed bus sequence control bit part b3 indicate 13°11'', that is, a data read cycle, the direction control signal 219 is set to "1" and the transmission direction of the buffer 203 on both sides of the multiplexed bus is set to the output side. At the same time,
A read signal 215 is output.

Therefore, by performing the above-described processing in the CPU mounting section 100, the multiplexed bus separation control section 202 outputs the lower address latch clock 2 to the lower address latch section 205.
18, and also sets the direction control signal 219 to 'O' to set the transmission direction of the multiplexed bus bidirectional buffer 203 to the input side. The lower address is launched into the lower address latch unit 205 via the external interface bidirectional breadthreader 107 multiplexed bus 4. multiplexed bus bidirectional buffer 203.

When the transfer of the lower address is completed, in order to transfer the upper address, the CPU 101 first sets the upper address to the multiplexed data output port 104, and then sets the multiplexed bus read bit part b1 of the multiplexed bus control signal output port 103. , multiplexed bus write bit section b2
"0°" is set in the multiplexed bus sequence control bit section b3, and information indicating the upper address cycle ("O", "1") is set in the multiplexed bus sequence control bit section b3. After that, the contents of the multiplexed bus write bit section b2 are set to "0°". ” to “1” and then back to “0”.

By performing the above processing in the CPU mounting section 100, the multiplexed bus separation control section 202 of the accessed section 200 applies the upper address rough clock 217 to the upper address latch section 204 and also outputs the direction control signal 21.
9 is set to "O" to set the transfer direction of the multiplexed bus bidirectional buffer 203 to the input direction. As a result, the upper address of the address at which CPUl0I executes the write operation is set in the upper address latch unit 204.

When the transfer of the upper address is completed, in order to write data, the CPU 101 first sets the write data in the multiplexed data output port 104, and then sets the multiplexed bus read focus section bl of the multiplexed bus control signal output port 103. .

The multiplexed bus write bit section b2 is set to 10'', and the multiplexed bus sequence control bit section b3 is set to 10''.
Information indicating the data write cycle (“1”, “0”)
After that, the contents of the multiplexed bus write bit section b2 are changed from 0'' to 1'', and then returned to 0.

By performing the above-described processing in the CPU mounting unit 100, the multiplexed bus separation control unit 202 in the accessed unit 200 sets the direction control signal 219 to 0'' and transmits the multiplexed bus bidirectional buffer 203. In addition to changing the direction to the input direction (thereby, the write data set in the multiplexed data output port 104 is transferred to the data bus 214 via the external interface bidirectional buffer 107, the multiplexed bus 4, and the multiplexed bus bidirectional buffer 203). )
, outputs a write signal 216.

Through the above operations, the write data and write signal 216 are output after the upper and lower addresses are determined, so these upper and lower addresses, write data, and write signal 2
By using 16, a normal write sequence can be performed.

Next, the operation when the CPUI O1 executes a read operation on the address space within the accessed unit 200 will be described.

When the CPUI O1 performs a read operation, the upper address latch section 204 . The upper address and lower address of the address to perform the read operation are set in the lower address latch unit 205.

Next, the CPUI O1 sets "O" in both the multiplexed bus read bit section b1 and the multiplexed bus write bit section b2 in the multiplexed bus control signal output port 103, and sets the multiplexed bus sequence control bit section b3 to "O". Information t[1 (“1”) indicating that it is a data read sequence.

After that, cput O1 changes the contents of the multiplexed bus read bit part b1 in the multiplexed bus control signal output port 103 from "0°" to "lo" and then returns it to "0". Let's do it.

By performing the above processing in the cpt7 mounting unit 101, the multiplexed bus separation control unit 202 in the accessed unit 200 sets the direction control signal 219 to “1” and changes the transmission direction of the multiplexed bus bidirectional buffer 203. is set in the output direction, and a read signal 215 is output. This results in
Data specified by the addresses latched in the upper address latch section 204 and lower address latch section 205 of the address space in the accessed section 200 is read out, and the data is read out from the data bus 214. Multiplexed bus bidirectional buffer 20
3. Multiplexed bus4. The multiplexed data is added to the manual port 105 via the external interface bidirectional buffer 107, and the multiplexed data input port 1 is added to the multiplexed data input port 1 at the time when the content of the multiplexed bus read bit section b1 changes from "work" to 0.
It is latched to 05. Therefore, by reading the multiplexed data input port 105 after performing the above-described processing, read data can be read.

〔Effect of the invention〕

As explained above, since the present invention multiplexes the address bus and the data bus, the number of interface lines between the CPU mounting section and the accessed section can be increased without reducing the capacity of the access space. It has the effect of reducing

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the invention. In the figure, 1,117,211...multiplex bus lead line, 2,118,212...multiplex bus write line,
3,119,213... Multiplexed bus sequence control line, 4... Multiplexed bus, 100... CPU mounting section, 101... CPU, 102... Decoder, 1
03...Multiplexed bus control signal output port, 1
04... Multiplexed data output port, 105... Multiplexed data input port, 106... External interface driver, 107... External interface bidirectional buffer, 111... Address bus, 112°214
...Data bus, 113...Write control signal line, 114...Read control signal line, 115
...Control port select signal, 116...
Data port select signal, 200... Accessed unit, 201... Multiplexed bus control signal reception buffer, 202... Multiplexed bus separation control unit, 203...
Multiplexed bus bidirectional buffer, 204... Upper address latch section, 205... Lower address latch section, 215
...Read signal, 216...Write signal, 217.
... Upper address latch clock, 218... Lower address latch clock, 219... Direction control signal, b
l... Multiplexed bus read bit section, b2... Multiplexed bus write bit section, b3... Multiplexed bus sequence control bit section.

Claims (1)

[Scope of Claims] In a system comprising a CPU mounting section equipped with a CPU and an accessed section accessed by the CPU mounting section, the CPU mounting section and the accessed section are connected by a multiplex bus,
Connected by a multiplexed bus read line, a multiplexed bus write line, and a multiplexed bus sequence control line, the CPU transfers data to the multiplexed data output port via the multiplexed bus to the accessed unit during an address cycle. The address is set, and information indicating an address cycle is set in the multiplexed bus control signal output port as multiplexed bus sequence control information to be transferred to the accessed section via the multiplexed bus sequence control line. Instructing write timing to the accessed unit via a multiplexed bus write line, and setting data to be transferred to the accessed unit via the multiplexed bus to the multiplexed data output port during a data write cycle; Information indicating a data write cycle is set in the multiplexed bus control signal output port as multiplexed bus sequence control information to be transferred to the accessed unit via the multiplexed bus sequence control line, and then the multiplexed bus Multiplexing that instructs write timing to the accessed section via a write line, and transfers the signal to the multiplexed bus control signal output port to the accessed section via the multiplexed bus sequence control line during a data read cycle. After setting information indicating a data read cycle as bus sequence control information, read timing is instructed to the accessed section via the multiplexed bus lead line, and the accessed section uses the multiplexed bus sequence control line. When the multiplexed bus sequence control information applied via the multiplexed bus indicates an address cycle, a write timing is instructed via the multiplexed bus write line, thereby causing the address applied via the multiplexed bus to be sent to the address latch section. and when the multiplexed bus sequence control information indicates a data write cycle, write timing is instructed through the multiplexed bus write line, and data applied via the multiplexed bus is latched to the address latch. When the multiplexed bus sequence control information indicates a data read cycle, read timing is instructed via the multiplexed bus lead line, and the address is latched in the address latch section. A CPU external access bus system, characterized in that data at an address is transferred to the CPU mounting section via the multiplexed bus.