JPH01194052A - Data input/output circuit for digital signal processing processor - Google Patents

Abstract

PURPOSE:To simultaneously execute access to an external memory and data I/O by using a dual port RAM as an external memory for a Digital Signal Processor (DSP). CONSTITUTION:The dual port RAM 2 (a RAM having two pairs of address and data writing/reading control terminals) is used for the external memory instead of a normal RAM and an address control circuit 4 for inputting/ outputting data through the dual port RAM 2 is also connected. Since the dual port RAM 2 is used for the external memory of the DSP 1, one data I/O terminal of the dual port RAM may be used for data I/O without directly executing data I/O through a DSP data bus. Consequently, data I/O from/to the external can be simultaneously executed even when the DSP accesses the external memory.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention is applicable to a special microprocessor used for digital signal processing, etc.
This relates to a circuit that inputs and outputs data to and from a cessor (hereinafter abbreviated as DSP).

[Conventional technology]

Figure 2 shows, for example, a paper presented at an IEEE international conference (Toshitaka T. et al.
“AHIGHPERFORM NCE LSI D
IGITAL 5IGN PROCESSOR
FORCOMMUNIC Tl0N ″Proc,
of ICC' 83 A5.

Fig. 6) is a configuration diagram showing the input/output circuit of the conventional DSP shown in Fig. 7, and in Fig. 2, (1) is the DSP.

(2) is this DSP (RA connected to 11
M (Random Access Memory),
(31 is a bidirectional buffer provided between the above D S P fl) and an external circuit, (5) is the above D S,
ROM (Read 0nl) connected to P fil
yMemory).

(11) is D S P + 11. Data bus signal line A, (13) connected to RAMf21 and buffer (3)
) is the data bus signal line C2 (14) connected to the external circuit and the upper buffer (3) is the RAM address signal line A;
(16) is the buffer control signal line, (17) is the ROM
The data signal line (18) is a ROM address signal line.

Next, the operation will be explained. ROM (511c +t
The command word of DSP (1) is stored as data, and the data at the address transmitted by the ROM address signal line (18) is transferred from the ROM (5) to the DSP (11) via the ROM data signal line (17). The data stored in the ROM (5) may include fixed (constant) data in addition to instruction words.D
The data to be processed by S P (11) is transferred from the external circuit to the data bus signal line C (13) via the buffer (3).
) and data bus signal line A (11).
given to fil. Conversely, the processing result is DSP
When outputting from (1) to an external circuit, data flows in the opposite direction along a similar path. In the input/output of data from such an external circuit to the DSP, data bus signal line A (11) and data bus signal @C (1
3) Control of the buffer located between
Control such as the direction during connection and transmission is performed by DSP (11) through the buffer control signal line (16).
A RAM (2) for storing data such as intermediate processing results of S P fil is connected to the data bus signal line A (11).

Data is exchanged with DSP (11) via the same signal line.The value of the address of RAM +21 at this time is:

Using the RAM address signal line (14), DSP (
14) to RAM (2).

[Problem to be solved by the invention]

Since the input/output circuit of a conventional digital signal processor (DSP) is configured as described above, it is necessary to control the data accessed to the external memory (RAM) of the DSP so that there is no conflict between the input/output data from the outside. Furthermore, access to the RAM and input/output of data cannot be performed at the same time, resulting in a large loss of time. Additionally, if data input/output and RAM access are to be performed simultaneously, DSP signal lines must be provided separately for input/output data and RAM, resulting in problems such as an increase in the number of DSP pins. there were.

This invention was made to solve the above-mentioned problems, and even in a DSP where the paths for RAM and data input/output are not separated, access to RAM and input/output of data can be performed simultaneously through the input/output circuit. The purpose is to obtain.

[Means to solve the problem]

The input/output circuit of the DIP according to the present invention uses a dual port RAM (2 terminals for address, data, and write/read control) instead of a normal RAM in the external memory.
In addition to using dual port R
It is provided with an address control circuit for inputting and outputting data via AM.

[For production]

In this invention, by using a dual port RAM as the external memory of the DSP, input/output is not performed directly through the data bus of the DSP, but instead uses one data input/output terminal of the dual port RAM. Bye. therefore.

It is also possible to simultaneously input and output data from the outside while the DSP is accessing the external memory.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) is DSP, (2) is DSP
(1) Dual port R connected as external memory
AM, (3) is the above dual port RAM (2)
A bidirectional buffer between the
4) is a control unit provided for address control of dual port RAM (21) and control of buffer (3);
(5) is a ROM connected to DSP (11), (1
1) is DSP (11 and dual port RAM
(2) Data bus signal line A provided between (12
) is a dual port, data bus signal @B provided between RAM (2) and buffer (3).

(13) is the data bus signal line C provided between the external circuit and the buffer (3), and (14) is the data bus signal line C provided between the external circuit and the buffer (3).
A RAM address signal @A is provided between the controller (4) and the dual port RAM (21), and a RAM address signal line B (15) is provided between the controller (4) and the dual port RAM (2).

(16) is the buffer control signal line provided between the control unit (4) and the buffer (3), (17) is the ROM +5)
The ROM data signal line (18) provided between the ROM address signal line and the ROM address signal line (18) is the same as the ROM address signal line.

Next, the operation will be explained. Here, first, dual port RA
Let's talk about M(2+.

A dual port RAM is a memory that has two opposing access systems for memory cells inside the memory, and has two sets of data and address terminals. In other words, it is different from normal RAM.

It has the characteristic that two independent systems can easily share memory. In the case of this embodiment, the configuration is such that the DSP (11) and the buffer (3) share this dual port RAM (2).When viewed from the DSP (1) side, the dual port RAM (2) functions as an external memory for the DSP, and functions as an input/output port for the DSP when viewed from the buffer (3), that is, the external circuit side.

In the case of this embodiment, in order to input data from an external circuit to the DSP fil, a specific address area of the dual port RAM+21 is first prepared for inputting data, and then the controller (4) Data is written via the buffer (3) to the address set through the address signal 1 (15).

At this time, the input data is transmitted through the data bus signal II (13) and the data bus signal line B (12), and the signal transmission direction of the buffer (3) is the buffer control signal line (16).
The control unit (4) gives an instruction through. Next, D S P [
11 is the address value of dual port RAM +21 (above specific area) through the RAM address signal line (14)
Set.

The data output from the memory is transferred to the data bus signal 1A (
11) Uke is taken through.

Conversely, in order to output data from the DSP (1) to the external circuit, first write data from the DSP (11) to the dual port, RAM+21, and then write the data to the dual port hRAM (21) through the buffer (3). The data path and individual operations are the same as for data input.

ROM (51, ROM data signal line (17) and ROM
The address signal line (18) operates in the same manner as the conventional technique explained using FIG. 2, so a duplicate explanation will be omitted.

〔Effect of the invention〕

As described above, according to the present invention, the simple configuration of using dual port RAM as the external memory of the DSP enables simultaneous access to the external memory and data input/output, and in order to avoid conflict between the two, No complicated design is required for hardware and DSP software.

[Brief explanation of the drawing]

FIG. 1 is a block diagram according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional configuration. (1) is DSP, (21 is dual port RA
M, (31 is a buffer, (4) is a control unit, (5) is an RO
M, (11) is a data bus signal line A, and (12) is a data bus signal line B. (13) is the data bus signal line C, (14) is the RAM address signal line A, (15) is the RAM7 F-less (No. i MB
, (16) is the buffer control signal line, (17) is the ROM
Data signal line, (18) is ROM address signal line. Note that the same reference numerals in the two figures indicate the same or equivalent parts.

Claims (1)

[Claims] A digital signal processing processor, a dual port RAM to which one data input/output terminal is connected to the data bus terminal of this digital signal processing processor, and a bidirectional buffer connected to the other data input/output terminal of this dual port RAM. . A data input/output circuit for a digital signal processing processor, comprising a control section that generates an address signal and a buffer control signal for one of the dual port RAMs for inputting and outputting data from an external circuit.