JPH01194052A - Data input/output circuit for digital signal processing processor - Google Patents

Data input/output circuit for digital signal processing processor

Info

Publication number
JPH01194052A
JPH01194052A JP1904288A JP1904288A JPH01194052A JP H01194052 A JPH01194052 A JP H01194052A JP 1904288 A JP1904288 A JP 1904288A JP 1904288 A JP1904288 A JP 1904288A JP H01194052 A JPH01194052 A JP H01194052A
Authority
JP
Japan
Prior art keywords
data
external memory
dual port
port ram
dsp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1904288A
Other languages
Japanese (ja)
Inventor
Hideaki Ebisawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1904288A priority Critical patent/JPH01194052A/en
Publication of JPH01194052A publication Critical patent/JPH01194052A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To simultaneously execute access to an external memory and data I/O by using a dual port RAM as an external memory for a Digital Signal Processor (DSP).
CONSTITUTION: The dual port RAM 2 (a RAM having two pairs of address and data writing/reading control terminals) is used for the external memory instead of a normal RAM and an address control circuit 4 for inputting/ outputting data through the dual port RAM 2 is also connected. Since the dual port RAM 2 is used for the external memory of the DSP 1, one data I/O terminal of the dual port RAM may be used for data I/O without directly executing data I/O through a DSP data bus. Consequently, data I/O from/to the external can be simultaneously executed even when the DSP accesses the external memory.
COPYRIGHT: (C)1989,JPO&Japio
JP1904288A 1988-01-29 1988-01-29 Data input/output circuit for digital signal processing processor Pending JPH01194052A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1904288A JPH01194052A (en) 1988-01-29 1988-01-29 Data input/output circuit for digital signal processing processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1904288A JPH01194052A (en) 1988-01-29 1988-01-29 Data input/output circuit for digital signal processing processor

Publications (1)

Publication Number Publication Date
JPH01194052A true JPH01194052A (en) 1989-08-04

Family

ID=11988367

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1904288A Pending JPH01194052A (en) 1988-01-29 1988-01-29 Data input/output circuit for digital signal processing processor

Country Status (1)

Country Link
JP (1) JPH01194052A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003078546A (en) * 2001-08-30 2003-03-14 Nec Eng Ltd Data processing circuit
KR100655544B1 (en) * 2005-01-11 2006-12-08 엘지전자 주식회사 External memory operating system based on multimedia mobile device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003078546A (en) * 2001-08-30 2003-03-14 Nec Eng Ltd Data processing circuit
KR100655544B1 (en) * 2005-01-11 2006-12-08 엘지전자 주식회사 External memory operating system based on multimedia mobile device

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