JPH02257241A - Memory access competition improving system - Google Patents

Abstract

PURPOSE:To prevent the access competition from being generated at the time of read-out of data by providing memory circuits corresponding to the number of processors, rewriting simultaneously each memory circuit at the time of write, and reading out of the memory circuit of the processor concerned at the time of read-out. CONSTITUTION:Processors 00, 10 hold dual port memories 02, 12 in common, and the dual port memory 02 can execute read-out only from the processor 00, and the dual port memory 12 can execute read-out only from the processor 10. Also, memory write can be executed to each of the dual port memories 02, 12 from both the processors 00, 10. In this regard, the processor 00 and the processor 10 have a local memory 01 and a local memory 11, respectively. In such a way, waiting at the time of a memory access is not generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to memory, and more particularly to a method for improving common memory access contention in multiprocessors.

[Conventional technology]

Traditionally, common memory access contention occurs when one side accesses (
(reading or writing), the other side waits to prevent conflicts from occurring.

[Problem to be solved by the invention]

As mentioned above, in the conventional access contention method for common memory, one side must always wait.As recent memories have become highly integrated, the above-mentioned waiting always occurs when accessing memory, making it difficult for the system to function. Throughput is decreasing.

[Means to solve the problem]

The memory access contention improvement method of the present invention is a memory circuit that is independently accessed by multiple processors, has memory circuits for the number of processors, and when writing, each memory circuit is rewritten simultaneously, and when reading, the memory circuit of the corresponding processor It is configured so that it can be read from.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, the memory access conflict improvement method is such that two white processors 00 and 10 share dual port memories 02 and 12, dual port memory 02 can be read only from processor OO, and dual port memory 12 can be read from processor 10. Memory writes are possible from both processors 00.10 to each of the dual port memories 02.12.

Note that the processor 00 has a local memory 01, and the processor 10 has a local memory 11.

Memory writing from processor 00 side is AND circuit 0
3 and 04 to the dual port memories 02 and 12. At this time, what is awaited is writing and reading from the processor 10 to the dual port memory. Here, since the same processor cannot do different things at the same time, no memory read signal is output from the processor 00 side at this time.

Further, memory reading from the processor 00 side is performed via the AND circuit 05 to the dual port memory O2. At this time, what is awaited is the write to the dual port memory from the processor 10 side.

Similarly, memory writing from the processor 10 side is AN
Dual port memory 02 via D circuits 13 and 14
, 12. At this time, what is awaited is writing and reading from the processor 00 side to the dual port memory.

Further, memory reading from the processor 10 side is performed to the dual port memory 12 through an AND circuit 15. At this time, what is awaited is the write to the dual port memory from the processor 00 side.

〔Effect of the invention〕

As explained above, the present invention prepares memory circuits for processors and allows data to be read from the memory for each processor individually when reading data. This eliminates access contention when reading data, and the system This has the effect of improving throughput.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. 00.10...Processor, 01.11...Local memory, 0,2,,,12...Dual port memory, 03.04,05.13.14.15...Logic circuit.

Claims (1)

[Claims] In a memory circuit that is independently accessed by multiple processors, it has memory circuits for the number of processors, and when writing, each memory circuit is rewritten at the same time, and when reading, the memory circuit is read from the memory circuit of the corresponding processor. Improvement method.