JPH08101812A - Bus interface device - Google Patents

Abstract

PURPOSE: To improve the use efficiency of an input/output device and an input/ output bus by eliminating the need for a dead cycle for evading a bus fight. CONSTITUTION: An address which should be outputted from a processor 100 to be input/output device 400 is temporarily transferred to a line address buffer 330 from an input/output bus address buffer 260 through an input/output bus 410. This transfer is controlled by an input/output bus interface control part 270 based on the instruction of an address transfer cycle indicator 230. Then an address data output selector 340 outputs data held in an input/output bus data buffer 320 or addresses held in a write address buffer 330 to the input/ output bus 410 in order. This address output is controlled by an input/output bus interface control part 270 based on the instruction of an address output cycle indicator 240.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus interface device for interfacing between a system bus and an input / output bus, and more particularly to efficiently write transactions from a processor on the system bus to an input / output device on the input / output bus. The present invention relates to a bus interface device for performing the operation.

[0002]

2. Description of the Related Art A bus interface device for connecting a system bus and an input / output bus may be mounted by being divided into a plurality of mounting units such as an address system and a data system depending on mounting requirements. That is, there are restrictions on the area and the number of input / output pins for mounting units such as boards and LSIs, and if these are not satisfied, it is necessary to divide the mounting units. The mounting units thus divided are normally synchronized with each other, but a slight deviation may occur due to clock skew or the like. Therefore, data from a plurality of mounting units may collide on the bus. Such collision of the data sent from the drivers on a plurality of mounting units on the bus is called a bus fight. When this bus fight occurs, the driver that sends data onto the bus may be destroyed. On the other hand, in the conventional technique, this bus fight is avoided by waiting for a certain period (hereinafter referred to as "dead cycle") of data transmission.

Referring to FIG. 7, in the prior art,
When the I / O bus is a bus for both address and data,
By providing a dead cycle (A2) between the sending of the address (A1) and the sending of the data (A3) onto the bus, the write transaction is executed to the input / output device while avoiding the bus fight. There is. When the I / O device cannot receive the write transaction, a retry response is sent to that effect (B1), and the address is again sent to the I / O bus (A1).
4), dead cycle (A5), and data transmission (A6).

Further, Japanese Patent Publication No. 4-61387 discloses that
There is described a technique for reducing the dead cycle to half of one cycle to speed up data transfer. In this technique, the dead cycle is reduced by transmitting the output permission timing after 1/2 cycle of the bus use permission signal by the data transmission period creating means.

[0005]

When the above-mentioned conventional technique is used, a dead cycle must be provided in order to avoid a bus fight when outputting to an address / data dual-purpose bus, and the I / O device There is a problem that the occupied time increases and the data processing time of the input / output device increases. Further, since a dead cycle is provided also during the retry response, there is a problem that the input / output device is occupied for a long time, the input / output bus is occupied for a long period, and the load on the input / output bus is increased.

Further, in the technique described in the above publication, although the dead cycle is shortened, there is a problem that the dead cycle is still required and it is not a fundamental solution.

An object of the present invention is to solve the above-mentioned problems, eliminate the need for a dead cycle for avoiding a bus fight, and improve the use efficiency of an input / output device.

Another object of the present invention is to improve the use efficiency of the input / output device and the input / output bus at the time of retry response.

[0009]

In order to solve the above-mentioned problems, a bus interface device according to the present invention comprises a first bus for connecting a first processing device for instructing writing, and a bus for writing by the first processing device. A second bus that connects the second processing device to be instructed, a bus interface device that mediates, and a first interface unit that mediates some information on the first bus; Second interface means for mediating information of the remaining part of the partial information on the first bus, wherein the first interface means transfers the partial information via the second bus. To the second interface means, and the second interface means sequentially outputs the partial information and the remaining information received from the first interface means to the second bus.

In another bus interface device of the present invention, a first bus connecting a first processing device for designating writing by designating an address and data, and a writing instruction by the first processing device. A bus interface device for mediating an address connecting the second processing device and a second bus that also serves as data, the address interface device mediating an address from the first bus; Data interface means for mediating data from the bus, the address interface means holds a first address holding circuit for holding an address from the first processing device and the first address holding circuit. The transfer of the assigned address to the data interface means and from the data interface means to the second bus. A bus control circuit for controlling the output of the address and data, wherein the data interface means includes a data holding circuit for holding data from the first processing device, and a second data holding circuit for holding an address from the address interface means. An address holding circuit, and a selector for sequentially outputting the address held in the second address holding circuit and the data held in the data holding circuit to the second bus, from the first processing device When writing is instructed to the second processing device, the bus control circuit transfers an address from the first address holding circuit to the second address holding circuit via the second bus. .

In another bus interface device of the present invention, when a bus control circuit receives a retry response from the second processing device, the bus control circuit stores the address held in the second address holding circuit and the data holding. The data stored in the circuit is controlled to be sequentially output to the second processing device via the second bus.

In another bus interface device according to the present invention, when a bus control circuit receives a retry response from the second processing device, the bus control circuit changes the address held in the first address holding circuit to the second address. Controlling the transfer of the address to the second address holding circuit via a bus, and then controlling the selector to output the address held in the second address holding circuit to the second bus. I do.

In another bus interface device according to the present invention, when a bus control circuit receives a retry response from the second processing device, the bus control circuit sends a response from the first address holding circuit to the second address holding circuit. The controller controls the selector to output the address held in the second address holding circuit to the second bus without transferring the address.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the bus interface device of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a bus interface device according to a first embodiment of the present invention includes a system bus 110.
And the input / output bus 410 are connected. System bus 110
(Hereinafter, also referred to as an S bus) is a split bus including an address and control signal bus 111 and a data bus 112, to which the processor 100 is connected. An input / output bus 410 (hereinafter, also referred to as an IO bus) is a multiplexer bus for both address and data, and an input / output device 400 is connected to it.

The bus interface device of this embodiment is divided into an address system 200 and a data system 300.
The address bus interface device 200 includes a system bus address command buffer 210 that receives and holds an address and a control signal from a system bus, and a system bus interface control unit that monitors signals on the system bus 110 and controls the bus interface device. 2
20, an address transfer cycle indicator 230 indicating that the cycle is to transfer the address, an address output cycle indicator 240 indicating that the cycle is to output the address, and a retry to the input / output device 400. Response control unit 250 for controlling the
An input / output bus address buffer 260 for holding an address to be output to the data bus interface device 10;
00 and the input / output device 400, and an input / output bus interface control unit 270 for performing timing control. The data bus interface device 300 is
A system bus data buffer 310 that captures and holds data on the system bus 110, and an input / output bus 410
Input / output bus data buffer 320 for holding data to be output to the I / O bus, write address buffer 330 for holding an address to be output to the I / O bus, and selecting one of the input / output bus data buffer 320 and the write address buffer 330 It has an address data output selector 340 for outputting on the input / output bus 410, and an address input buffer 350 for receiving an address via the input / output bus 410.

System bus interface control section 220
Checks the control signal on the system bus input from the system bus address command buffer 210 via the signal line 211. Then, according to the result, the system bus interface control unit 220 causes the system bus address command buffer 210, the address transfer cycle indicator 230, or the system bus data buffer 3 to operate.
An instruction to be described later is given to 10.

Input / output bus interface controller 270
Responds to the instructions from the address transfer cycle indicator 230 and the address output cycle indicator 240 to instruct the I / O bus address buffer 260 to output an address and to output an address data output selector 340
Alternatively, fetching an address from the input / output bus 410 to the address input buffer 350 or input / output bus 41
Instruct output to 0.

The retry response control section 250 receives the input / output device 400 via the input / output bus interface control section 270.
When the retry response is received from, a notification to that effect is sent to the address output cycle indicator 240.

The address data output selector 340 selects one of the input / output bus data buffer 320 and the write address buffer 330 in accordance with an instruction from the input / output bus interface control unit 270 via the address output cycle notification line 273. Output to the input / output bus 410.

The address input buffer 350 responds to an instruction from the input / output bus interface control unit 270 via the address transfer cycle notification line 274,
The address on 10 is taken.

Next, the operation of the first embodiment of the bus interface device according to the present invention will be described with reference to the drawings.

Referring to FIGS. 1 and 2, first, when a control signal, an address and data are output from the processor 100 onto the system bus 110, the control signal and the address on the bus 111 are transferred to the system bus address command buffer 210. The data on the bus 112 is held in the system bus data buffer 310.

System bus interface control section 220
When it is determined from the control signal held in the system bus address command buffer 210 that the request from the processor 100 is a write transaction to the input / output device 400, the request from the system bus address command buffer 210 to the input / output bus address buffer 260 The transfer of the address is instructed by the signal line 211. Thus, the address held in the system bus address command buffer 210 is stored in the input / output bus address buffer 2.
It is transferred to 60 and held.

The system bus interface control unit 220 instructs data transfer from the system bus data buffer 310 to the input / output bus data buffer 320 via the data fetch notification line 229. As a result, the data held in the system bus data buffer 310 is transferred to and held in the input / output bus data buffer 320.

Referring to FIGS. 1 to 3, address transfer cycle indicator 230 asserts address transfer cycle notification line 274 when notified of a write transaction to input / output device 400 from system bus interface control section 220. To the input / output bus interface control unit 270 to perform the operation. As a result, the input / output bus interface control unit 270 asserts the address transfer cycle notification line 274 (J1, step 501).

Input / output bus interface controller 270
Transmits the address stored in the input / output bus address buffer 260 via the signal line 271 to the input / output buffer 41.
Instruct to output on 0. Thereby, the input / output bus address buffer 260 outputs an address on the input / output bus 410 (L1, step 502). The input / output bus interface controller 270 further asserts the address transfer cycle notification line 274 to fetch the address on the input / output bus 410.
Instruct. The address input buffer 350 fetches an address from the input / output bus, and further holds this address in the write address buffer 330 (step 50).
3).

When the address output cycle indicator 240 is informed of the address transfer cycle from the address transfer cycle indicator 230, the input / output bus interface controller 270 causes the address output cycle notification line 273 to be asserted next. To give instructions. Thereby, the input / output bus interface control unit 270 asserts the address output cycle notification line 273 (M1, step 504).

When the address data output selector 340 recognizes that the address output cycle is due to the assertion of the address output cycle notification line 273, it outputs the address held in the write address buffer 330 onto the input / output bus 410. (L2, Step 50
5). After that, the address data output selector 340
The data held in the input / output bus data buffer 320 is output onto the input / output bus 410 (L3, step 50).
6). As a result, a write transaction to the input / output device 410 can be executed.

Input / output bus interface controller 270
Monitors the I / O bus 410 to determine whether the write transaction to the I / O device 400 has succeeded. As a result, when the input / output device 400 cannot receive the write transaction, the fact is notified from the input / output bus interface control unit 270 to the retry response control unit 250 (step 507). The retry response control unit 250 includes the address transfer cycle indicator 230
To instruct an address transfer cycle.

In response to the notification from the retry response control unit 250, the address transfer cycle indicator 230 instructs the input / output bus interface control unit 270 to assert the address transfer cycle notification line 274. Thereafter, similarly to the first, the input / output bus interface control unit 270 asserts the address transfer cycle notification line 274 (J2, step 501), whereby the address is output on the input / output bus 410 (L4, step 502). ), This address is held in the write address buffer 330 (step 503). Then, the address output cycle notification line 273 is asserted (M2,
Step 504). Then, the address (L5, step 505) and the data (L6,
Step 506) is sequentially output. This makes it possible to execute a retry process for a write transaction to the input / output device 410.

As described above, according to the bus interface device of the first embodiment of the present invention, the address to the input / output device 400 is transferred to the address bus interface device 200.
From the data system bus interface device 300 to the data system bus interface device 300, addresses and data can be continuously output from the data system bus interface device 300 to avoid a dead cycle. Thereby, the input / output device 400 can be used efficiently.

Next, a second embodiment of the bus interface device of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 4, the bus interface device according to the second embodiment of the present invention is the same as that shown in FIG. 1 except that the output of the retry response controller 250 is input to the address output cycle indicator 240. It has the same configuration as that of the first embodiment. Upon receiving the retry response from the input / output bus interface control unit 270, the retry response control unit 250 notifies the address output cycle indicator 240 to instruct an address output cycle. On the other hand, the point that the address output cycle indicator 240 issues an instruction to the input / output bus interface controller 270 is the same as in the first embodiment.

Next, the operation of the second embodiment of the bus interface device according to the present invention will be described with reference to the drawings.

Referring to FIGS. 4 to 6, the processing up to the retry response is the same as in the first embodiment. Therefore,
Hereinafter, processing after the retry response will be described.

When retry response control section 250 notifies address output cycle indicator 240 to instruct an address output cycle, address output cycle indicator 240 causes input / output bus to assert address output cycle notification line 273. An instruction is given to the interface control unit 270. As a result, the input / output bus interface control unit 270 sets the address output cycle notification line 27
3 is asserted (M2, step 604). That is, at the time of retry, the address is not transferred from the address bus interface device 200 to the data bus interface device 300 (steps 601 to 603).
Use the address transferred before the retry again.

Subsequent processing is the same as in the first embodiment, and an address (L5, step 605) and data (L6, step 606) are sequentially output to the input / output bus 410. This makes it possible to execute a retry process for a write transaction to the input / output device 410.

As described above, according to the bus interface device of the second embodiment of the present invention, in the retry processing, the address transferred before the retry is different from that of the first embodiment. Is used again, the address transfer from the address bus interface device 200 to the data bus interface device 300 can be omitted, and the use efficiency of the input / output bus 410 can be improved.

[0040]

As is apparent from the above description, according to the present invention, the address to the input / output device is temporarily transferred to the data bus interface device, so that the error occurs between the address and the data. It is possible to avoid the dead cycle and improve the usage efficiency of the input / output device.

In the retry process, the address transferred before the retry is used again, so that the address transfer to the data bus interface device is not performed again, and the efficiency of use of the input / output bus is improved. Can be done.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a bus interface device of the present invention.

FIG. 2 is a diagram illustrating an operation of the bus interface device according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating an operation procedure of the bus interface device according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a second embodiment of the bus interface device of the present invention.

FIG. 5 is a diagram illustrating an operation of a bus interface device according to a second embodiment of the present invention.

FIG. 6 is a diagram illustrating an operation procedure of a bus interface device according to a second embodiment of the present invention.

FIG. 7 is a diagram illustrating an operation of a bus interface device according to the related art.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 processor 110 system bus 200 address bus interface device 210 system bus address command buffer 220 system bus interface controller 230 address transfer cycle indicator 240 address output cycle indicator 250 retry response controller 260 input / output bus address buffer 270 input / output bus Interface controller 300 Data bus interface device 310 System bus data buffer 320 I / O bus data buffer 330 Write address buffer 340 Address data output selector 350 Address input buffer 400 I / O device 410 I / O bus

Claims (4)

[Claims] 1. A first bus connecting a first processing device for instructing writing, and a second bus connecting a second processing device for instructing writing by the first processing device. A mediating bus interface device, comprising: a first interface means for mediating a part of information on the first bus; and a first interface means for mediating a remaining part of the information on the first bus. A second interface means, the first interface means transfers the part of the information to the second interface means via the second bus, and the second interface means includes the second interface means. A bus interface device, wherein the partial information and the remaining information received from one interface means are sequentially output to the second bus. 2. A first bus for connecting a first processing device that instructs writing by designating an address and data, and a second processing device for which writing is instructed by the first processing device. In a bus interface device that mediates an address and a second bus that also serves as data, an address interface unit that mediates an address from the first bus, and a data interface unit that mediates data from the first bus The address interface means includes: a first address holding circuit that holds an address from the first processing device; and a transfer of the address held by the first address holding circuit to the data interface means. Bus control for controlling and controlling the output of addresses and data from the data interface means to the second bus A data holding circuit for holding data from the first processing device, a second address holding circuit for holding an address from the address interface means, A selector for sequentially outputting the address held in the address holding circuit and the data held in the data holding circuit to the second bus, from the first processing device to the second processing device. A bus interface device, wherein when a write is instructed, the bus control circuit transfers an address from the first address holding circuit to the second address holding circuit via the second bus. 3. The bus control circuit, upon receiving a retry response from the second processing device, transfers the address held in the first address holding circuit to the second address via the second bus. 3. The control circuit according to claim 2, further comprising: controlling the transfer of an address to a holding circuit; and controlling the selector to output the address held by the second address holding circuit to the second bus. A bus interface device as described. 4. When the bus control circuit receives a retry response from the second processing device, the bus control circuit does not transfer an address from the first address holding circuit to the second address holding circuit. 3. The bus interface device according to claim 2, wherein the selector controls the selector to output the address held in the second address holding circuit to the second bus.