JPS60186955A - Dma control system - Google Patents

Abstract

PURPOSE:To reduce the load on a CPU for peripheral LSI control and to attain a high throughput by detecting a signal which indicates the DMA cycle of final data outputted from a controller. CONSTITUTION:The level of a signal line 9 is checked when the level of a signal line 10 becomes high and a DMA cycle is entered. The level is high, so an LSI control circuit 5 judges that the DMA cycle of final data is entered. Then, a control signal sent out of a DMA controller 4 is not outputted to a control bus 12 and a command to be written in a peripheral LSI13 is outputted to a data bus 13. Then, the signal on the control bus for writing data in the peripheral LSI3 is held low to write the data in the peripheral LSI3. At this time, the signal on the control bus 12 for reading data to be written in the peripheral LSI3 out of memory 2 is expected to be low, but held high by the LSI control circuit 5.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) This invention relates to a DMA of a microcomputer peripheral LSI.
Regarding control method.

(Background Art) In recent years, microcomputers have been increasingly used in control devices and the like, and as a result, many peripheral LSIs that are connected to microcomputers and perform control have come on the market.

Control methods for peripheral LSIs for microcomputers, which are typically used to control external devices and transfer data, include program control methods and DMA (direct memory access).
cess ) control method.

In the program control system, as shown in FIG. 1, a central processing unit (hereinafter referred to as CPU) 1, a memory (MEM) 2, and a peripheral LSI 3 are connected by a data bus 13 and a control bus 12, and the data of the 2 peripheral LSIs 3 is read out. and write, command write and status read to CP
In this method, the UI directly controls the control bus 12 and performs control via the data bus 13.

The DMA control system consists of a CPU 1, memory 2, DMA controller (DMA-C) 4, and peripheral L as shown in Figure 2.
The SI 3 is connected to the data bus 13 and the control bus 12, and the CPU 1 controls the control bus 12 and reads the status to the peripheral LSI 3 via the data bus 13.
In this system, the DMA controller 4 receives the right to use the control bus 12 from the CPUI and transfers data to and from the memory 2 via the data bus 13.

Recently, due to high throughput requirements, C
There is a demand for reducing the PU load, and there is a tendency to use a DMA control method rather than a program control method. In particular, many peripheral LSIs intended for data transfer use a DMA control method in order to free the CPU from multiple reads and writes between memory and internal registers of the peripheral LSI.

In peripheral LSIs for program control, even if a data request signal is used as a signal to operate a DMA controller, the CPU may need to write a data transfer end instruction by detecting the end of a data block. Yes, it could not be said to be a perfect MA control system.

Furthermore, even with peripheral LSIs for DMA control, there are some that require the CPU to directly write the end r of a data block to the peripheral LSI, depending on the setting of the mode used.

(Object of the Invention) The present invention has been made by focusing on such conventional problems, and is intended to provide a C
It is possible to complete the DMA control of the peripheral LSI without the intervention of the PU, and as a result, the C for controlling the peripheral LSI can be completed.
DMA that reduces PU load and achieves high throughput
The purpose is to provide a control method.

A feature of the present invention for achieving this object is that the invention includes a central processing unit, a memory, a DMA controller, a peripheral device, and a peripheral LSI that requires a data transfer end instruction from the central processing unit when performing data transfer. The peripheral LSI is granted the right to use the data bus and control bus for the central processing unit to read and write data to and from the memory and peripheral LSI.
By temporally switching between the central processing unit and the DM-A controller depending on the presence or absence of a data request signal from the SI, the DMA controller controls data transfer between the peripheral LSI and the memory using the same bus. In the processing device, an LSI control circuit for instructing the peripheral LSI to complete data transfer during the final data transfer cycle of a data block is connected to the DMA controller and the CPU.
and the peripheral LSI, and the LSI control circuit is connected to the D
Obtaining the right to use the data bus and the control bus during the final data DMA cycle from the DMA controller by detecting a signal indicating that it is the final data DMA cycle output from the MA controller,
DM to write the data transfer end instruction to the peripheral LSI
It is in A control method.

(Structure and operation of the invention) FIG. 3 is a block diagram showing an embodiment of the DMA control method according to the invention. 1 is the CPU, 2 is the memory (ME
M), 3 is a peripheral LSI that transfers data to a peripheral device (not shown) and requires the CPU to instruct the end of data transfer immediately before sending the final data; 4 controls DMA transfer between peripheral LSI 3 and memory 2; DMA controller (
DMA-C), 5 is the peripheral L at the time of DMA transfer of the final data.
The LSI control circuit (L
SI-C). These blocks are connected to control bus 12 and data bus 13 as shown. In particular, the control signal of the DMA controller 4 is supplied to the LS control circuit 5 via the bus 11, and is used as a control signal of the LSI control circuit 5, or is used as it is, depending on whether it is a final data DMA transfer or not. =ry is supplied to the troll bus 12. The signal line 6 is
A data request signal from the peripheral LSI 3 is transmitted to the DMA controller 4. The signal line 7 transmits a request signal for the right to use the control bus 12 and data bus 13 from the DMA controller 4 to the CPUI. The signal line 8 transmits a response signal to this request signal to the DMA controller 4.

The signal line 9 transmits a signal from the DMA controller 4 to the LS that indicates whether the data in the DMA transfer is the final data.
It is transmitted to the I control circuit 5. The signal line 1O transmits a signal indicating whether or not it is a DMA cycle from the DMA controller 4 to L.
The information is transmitted to the SI control circuit 5.

Next, the operation will be explained using the operation timing diagrams shown in FIGS. 4 and 5. FIG. 4 is an operation timing diagram when the final data is not transferred by DMA, and FIG. 5 is an operation timing diagram when the final data is transferred by DMA.

The CPU writes a command that must be written to the peripheral LSI 3 at the end of the data block into a register in the LSI control circuit 5. Next, the DMA controller 4 is set in order to write the contents of the memory 2 to the peripheral LSI. Thereafter, the peripheral LSI 3 is initialized and data transfer is started.

When the peripheral LSI 3 is ready to send data to the peripheral device, it sends a data request signal to the DMA controller 4 by setting the level of the signal line 6 to high to request data (FIG. 4(a)). In response to this, the DMA controller 4 requests the CPUI for the right to use the control bus 12 and data bus 13 by setting the level of the signal line 7 high, and waits for these buses to be released. At this time, if the data transfer is not the final data transfer, the level of the signal line 9 is kept low (Fig. 4(c)), the CPU 1 enters the hold state at the cycle break, and the controller The bus 12 and data bus 13 are released, and a response signal to the request for the right to use these buses is sent by setting the level of the signal line 8 to high. As a result, the DMA controller 4 receives the right to use the control bus 12 and the data bus 13, and sends out a signal indicating that a DMA cycle has started by setting the level of the signal line 10 to high. When the level of the signal line IO becomes high, the LSI control circuit 5 checks the level of the signal line 9 to determine whether or not it is the final data transfer.As mentioned above, the level of the signal line 10 is Since it is not a transfer of raw or final data, the LSI
The control circuit 5 is a control signal sound sent from the DMA controller via the bus 11, and it is a control bus! Output to 2. As a result, data bus 3 is read out from memory 2 by a signal in control bus 12 (FIG. 4(e)) for reading data to be written to one peripheral LSI 3 from memory 2 according to a normal DMA cycle. The above data (FIG. 4(f)) is transferred to the data bus 13-
The signal in the control bus 12 (FIG. 4(d)) for writing the data of 1 to the peripheral LSI 3 causes the peripheral LSI to
5 is written.

Now, when the data transferred from the memory 2 is the final data, a data request signal is output from the peripheral LSI 3 to the DMA controller 4 (FIG. 5(a)), and the DMA
When the controller 4 outputs a request for the right to use the control bus 12 and data bus 13 to the CPUI, the DMA controller 4 sets the level of the signal line 9 to high (pfSS diagram (C)), and sets the level of the signal line IO to high. When the level becomes high and a DMA cycle begins (FIG. 5(b)), the level of the signal line 9 is checked as described above. Since the level of the signal line 9 is high, the LSI control circuit 5 determines that the final data DMA cycle has entered,
The control signal sent from the DMA controller 4 via the bus 11 is not outputted onto the control bus 12, but the command to be written to the peripheral LSI 3 is outputted onto the data bus 13 (FIG. 5(f)), so that the data is not outputted onto the peripheral LSI 3. Signals in the control bus for writing to LSI3 (Figure 5(d)
) is set to low to write to the peripheral LSI 3. At this time, the data to be written to the peripheral LSI 3 is transferred to the memory 2.
The signal in the control bus 12 for reading from the fifth
In Figure (e), the LSI control circuit 5 keeps the low level (broken line portion) high.

Thereafter, by setting the level of the signal in the control bus 12 to low as shown in FIG. 5(e), the data on the data bus 13 (FIG. 5(r)) read from the memory 2 is
The data is written to the peripheral LSI 3 by setting the level of the signal in the control bus 12 shown in the ms diagram (d) to low.

(Effects of the Invention) As explained above, according to the present invention, it is possible to complete DMA control of a peripheral LSI that requires data block termination control without the intervention of the CPU. This has the effect of reducing the CPU load for controlling one peripheral LSI and achieving high throughput.

'Furthermore, since the present invention is capable of DMA transfer, it can be used for high-speed data transfer.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional program control system;
Figure 3 is a block diagram of a conventional DMA control system, Figure 3 is a block diagram of an embodiment of the DMA control system according to the present invention, and Figure 4 is an operation timing diagram when the data to be transferred is not the final data in Figure 3. , and FIG. 5 are operation timing diagrams when the data to be transferred in FIG. 3 is the final data. 1-m-central processing unit (CPU), 2-m-memory (MEM), 3--one peripheral LSI (LSI), 4--one DMA controller (DMA-C), 5-
--LSI control circuit (LS I-C), 8, 7. El
, 9.10---One signal line, 11-m-bus, 12
-m-control bus, 13-m-data path. Patent applicant Oki Electric Industry Co., Ltd. Patent application agent Megumi Yamaki - Figure 4 +f+ (DATA) -1--i, □t11--
- Figure 5 Mountain (TA procedure amendment to D (voluntary) August 14, 1980 Commissioner of the Patent Office Shiga Means 1 Display of the case 1983 Patent application No. 40542 2 Name of the invention DMA control method 3, amendment Relationship with the case of the person who made the amendment Patent applicant name (February Oki Electric Industry Co., Ltd. 4 Agent 5, Detailed description of the invention column and drawing 6 of the specification subject to amendment, Contents of amendment 11) Specification No. 3 Correct “controller” on the 15th line of the page to “1 controller”. (2) Correct “L8I5J” on the additional line of the 9th page of the specification to [L8I3
Correct with J. (3) Figure 2 of the drawings shall be amended as shown in the attached sheet. that's all

Claims (1)

[Claims] It has a central processing unit, a memory, a DMA controller, and a peripheral LSI that requires a data transfer end instruction from the central processing unit when data is transferred to the peripheral device, and the central processing unit reads and writes data to and from the memory and peripheral LSI. By temporally switching the right to use the data bus and control bus between the central processing unit and the DMA controller depending on the presence or absence of a data request signal from the peripheral LSI, In a processing device in which a controller controls data transfer between a peripheral LSI and a memory, the DMA controller includes an LSI control circuit for instructing the peripheral LSI to complete data transfer during the final data transfer cycle of a data block;
The LSI control circuit is provided between the CPU and the peripheral LSI, and the LSI control circuit receives the final data output from the DMA controller.
By detecting a signal indicating that it is an MA cycle, the right to use the data bus and control bus is obtained from the DMA controller during the final data DMA cycle, and a data transfer end instruction is written to the peripheral LSI. Features I) MA control method.