JP2000155738A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processor capable of speeding up the system even if sufficient memories can not be secured for both a system bus and an I/O bus by connecting and disconnecting both buses according to whether or not DMA transfer is in process. SOLUTION: This data processor which sends and receives data to and from an external device by DMA transfer is equipped with a 1st bus line 2 to which a CPU 1 is connected, a DMA control means 3 which controls the DMA transfer, a storage means 4 which stores data sent and received by the DMA transfer, a 2nd bus line 5 to which the DMA control means and storage means are connected, and a connection/disconnection arbitrating means 6 which is interposed between the 1st and 2nd bus lines and connects and disconnects the 1st and 2nd bus lines.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus for transmitting and receiving data to and from an external device by DMA transfer, and more particularly, to a bus line connected to a CPU and a DMA.
And a bus line connected to a memory for storing data to be transmitted and received by transfer.

[0002]

2. Description of the Related Art One of the devices for performing data processing using a computer is an office automation (OA) device. In recent years, the amount of data to be processed by this OA device has been increasing due to demands for colorization, high speed, and high resolution. To handle such data, the amount of data transferred from the input / output device by DMA (direct memory access) is increasing. In order to cope with this increase in the amount of data, the width of the system bus is widened so that a large amount of data can be transmitted and received at one time, or the clock is advanced so that a large amount of data can be transmitted and received in a fixed time. In addition to these actions,
In order to reduce the amount of data transferred by the system bus to which the CPU is connected, a memory area for data to be subjected to DMA transfer is not provided on a memory area for the system bus, but is provided on another bus such as an I / O bus. (Japanese Patent Laid-Open No. 9-20439).
No. 1).

[0003]

The above-mentioned JP-A-9-20
The method proposed in US Pat.
In a system that can secure a sufficient memory for data transferred by both O buses, it is effective as a method for processing data at high speed. However, it is not possible to secure a sufficient memory for data transferred by both the system bus and the I / O bus, or a memory for storing system data and a memory for storing DMA data for a small-scale system. In the case where it is necessary to share a memory or to process data transferred from an external I / O device through a CPU, the method proposed above may be adopted. High-speed processing of data could not be achieved. In view of the above, the present invention has been made in view of the above points, and a sufficient memory is secured in both buses by connecting or disconnecting both a system bus and an I / O bus depending on whether or not a DMA transfer is being performed. It is an object of the present invention to provide a data processing device capable of increasing the speed of the entire system even if it cannot be performed.

[0004]

According to the first aspect of the present invention, there is provided a data processing apparatus for transmitting and receiving data to and from an external device by DMA transfer, comprising: A bus line, a DMA control unit for controlling DMA transfer, a storage unit for storing data transmitted and received by DMA transfer, a second bus line connecting the DMA control unit and the storage unit, A connection / separation arbitration means for connecting or separating the first bus line and the second bus line between the bus line and the second bus line; In the data processing device according to the first aspect of the present invention, the connection / separation arbitration unit may transmit and receive the image data via the second bus line by DMA transfer. The line and the second bus line are separated. Claim 3
In the data processing device according to the first or second aspect of the present invention, when the access from the CPU to the storage unit and the access to the storage unit for writing transmission / reception data by DMA transfer are simultaneously performed, The contact / separation arbitration unit is configured to control the CP of the access denied.
U or the DMA control means is set to a WAIT state.

According to the first aspect of the present invention, the first bus line and the second bus line can be connected or separated by the connection / separation arbitration means. When both bus lines are connected, the CPU can access the storage means connected to the second bus line, and it is necessary to have storage means for storing data on the first bus line side. Disappears. When both bus lines are separated, the first bus line and the second bus line can perform independent operations in parallel. According to a second aspect of the present invention, in addition to the data processing apparatus of the first aspect, while the data is being transmitted and received through the second bus line by the DMA transfer, the connection / separation arbitration means is provided. The first bus line and the second bus line are separated from each other.
U can access devices on the first bus line. According to a third aspect of the present invention, in addition to the data processing apparatus of the first or second aspect, when the CPU and the DMA control means simultaneously access the storage means, the connection / separation arbitration means is provided. , The CPU or the DMA control means which has denied access
State, the CPU or the DMA control means can access the storage means without being conscious of the separation state between the first bus line and the second bus line, thereby providing an efficient system. Can be provided.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing a main part of an image processing apparatus 20 which is a typical example of a data processing apparatus according to the present invention. In the figure, CPU 1
ROM 9 mainly storing program software and CPU 1
Has a function as a system control unit that controls the entire system between the units of the image processing apparatus 20 integrally with the sub-memory 8 that is configured by a RAM that temporarily stores the calculation results and the like. Specifically, it determines the operation timing of each unit of the image processing apparatus 20, checks whether each unit is operating normally, detects an error that has occurred in each unit, and displays an error on a display unit (not shown). Display. A font for character display is stored in a part of the ROM 9. Further, the image processing unit 7 performs image processing on the image data received from the external device according to the already set setting conditions, and converts the image data into printable data such as binary bit data. The processed image data is printed by an image forming unit (not shown) or the like. Here, the CPU 1, the sub memory 8, the ROM 9, the image processing unit 7, and the like are connected to the system bus 2, which is a first bus line. The system bus 2 can be said to be a bus line for performing image processing mainly on the CPU 1. In addition, an I / O (Input Output) bus 5, which is a second bus line, includes:
An external interface (I / F) 10 for transmitting and receiving data to and from the external device 21, a DMA control unit 3 for enabling image data to be transmitted and received to and from the external device 21 by DMA transfer, and storing image data to be transmitted and received. The main memory 4 serving as a storage unit is connected. I / O bus 5
Is a bus line for mainly transmitting and receiving data to and from the external device 21.

[0007] A connection / separation arbitration unit 6 is provided between the system bus 2 and the I / O bus 5 for connecting and disconnecting both buses. Further, the contact / separation arbitration unit 6
Are connected to the system bus 2 by a system arbitration bus 11 and connected to the I / O bus 5 by an I / O arbitration bus 12. For example, the system bus 2
When the I / O bus 5 is connected to the
I / O from the system bus 2 via the connection / separation arbitration unit 6
Accessing the main memory 4 via the bus 5;
Alternatively, the external device 2 through the external interface 10
1 can be accessed. In order to access the main memory 4 from the CPU 1, a CPU contact / separation signal line 13 is connected between the CPU 1 and the contact / separation arbitration unit 6.
Further, a DMA is provided between the DMA control unit 3 and the contact / separation arbitration unit 6.
The contact / separation signal line 14 is connected.
DMA from the DMA control unit 3 via the MA contact / separation signal line 14
When the transfer start information is received, the system bus 2 and the I / O
The bus 5 is separated.

In a state where the system bus 2 and the I / O bus 5 are separated, image data from the external device 21
Under the control of the A control unit 3, the external interface 10
Via the I / O bus 5 and written in the main memory 4 by DMA transfer. The image data stored in the main memory 4 is transmitted to the I / O under the control of the DMA controller 3.
DMA via bus 5 and external interface 10
It is transferred to the external device 21 by transfer. The above I / O bus 5
During the DMA transfer via the I / O, the system bus 2 and the I / O
Since the bus 5 is in a separated state, the CPU 1 can issue a command to each device connected to the system bus 2 to proceed with image processing. For example, one copy of the image data taken into the sub-memory 8 is converted into data in a format to be printed by the image processing unit 7, or a corresponding font is searched for from the fonts stored in the ROM 9. As in this case, the sub memory 8 stores the CPU 1
It is only necessary to store the result of the calculation in the middle or to store a part of the image data during the image processing, so that a very small capacity is sufficient compared with the capacity of the main memory 4.

FIG. 2 is a block diagram showing the contact / separation arbitration unit 6 in FIG. 1 in more detail. In addition, the operation of FIG. 2 will be particularly described only for the contact / separation arbitration unit 6, and the other operations are the same as those described with reference to FIG. In the figure,
The contact / separation arbitration unit 6 is roughly composed of a contact / separation arbitration control unit 6a and a contact / separation execution unit 6b. The above-described system arbitration bus 11 includes a system bus control line 11a and a system bus connection / disconnection line 11b.
The / O arbitration bus 12 is connected to the I / O bus control line 12a and the I / O bus
It is composed of an O contact / separation line 12b. The system bus control line 11a and the I / O bus control line 12a are connected to both ends of the connection / separation arbitration control unit 6a so that the state of the system bus 2 and the I / O bus 5 can be constantly monitored by the connection / separation arbitration control unit 6a. Has become. Further, the contact / separation arbitration control unit 6a
, The CPU contact / separation signal line 13 is connected to the CPU 1 and the DMA contact / separation signal line 14 is connected to the DMA controller 3. The system bus contact / separation line 11b and the I / O contact / separation line 12b constitute a part of the contact / separation execution unit 6b, and actually connect or separate the system bus 2 and the I / O bus 5. It is in charge of bridging action.

Next, the operation of the contact / separation arbitration unit 6 will be described in detail with reference to a block diagram. The main configuration of the contact / separation execution unit 6b is composed of two gate circuits 6b placed in parallel in opposite directions as shown in the figure.
1, 6b2. Two gate circuits 6b1,
6b2 is configured such that each output terminal is connected to the other input terminal, and bus connection signal lines 6b4 and 6b5 are output from both ends of the gate circuits 6b1 and 6b2. Also,
The two gate circuits 6b1 and 6b2 have a gate signal line 6b3 for controlling ON / OFF of the two gate circuits connected to the connection / separation arbitration control unit 6a. Such gate circuits 6b1 and 6b2 and bus connection signal lines 6b4 and 6b5
And the number of gate signal lines 6b3 in the connection / separation execution unit 6b required for connecting the system bus 2 and the I / O bus 5. The contact / separation arbitration control unit 6a
Can receive a DMA transfer request command and DMA transfer start information via the CPU contact / separation signal line 13 and the DMA contact / separation signal line 14. In this manner, the connection / separation arbitration control unit 6a, which has learned that the DMA transfer has started, sets the gate signal line 6b3 to the high state. Gate signal line 6b3
Are in a high state, the gate circuits 6b1 and 6b2 are turned on, and both ends of the gate circuits 6b1 and 6b2 are turned on, so that the I / O buses 5 and I / O
Information can flow from the O bus 5 to the system bus 2.

Further, upon receiving a notification from the DMA control unit 3 that the DMA transfer has been completed, the contact / separation arbitration control unit 6a sets the gate signal line 6b3 to a low state. Gate signal line 6b
When 3 is in the Low state, the gate circuits 6b1 and 6b2 are turned off, the both ends of the gate circuits 6b1 and 6b2 are turned off, and the system bus 2 and the I / O bus 5 are separated. The contact / separation arbitration control unit 6 a accesses the main memory 4 from the CPU 1 and the access from the DMA control unit 3 to the main memory 4 via the CPU contact / separation signal line 13 and the DMA contact / separation signal line 14. Can be detected at the same time. When the access to the main memory 4 from the CPU 1 and the DMA control unit 3 is performed at the same time as described above, the connection / separation arbitration control unit 6a sets the CPU 1 or the DMA
One of the control units 3 is set to the WAIT state, and the main memory 4
Waiting for access to. For example, CP
If the access to the main memory 4 from the U1 and the DMA control unit 3 is performed simultaneously and the access to the main memory 4 from the CPU 1 cannot be performed, the connection / separation arbitration control unit 6
a, the CPU 1 is connected to the WAI via the CPU contact / separation signal line 13;
In the T state, access to the main memory 4 is waited. Conversely, the main memory 4 from the DMA control unit 3
If access to the server is not possible, the contact / separation arbitration control unit 6a
Sends the DMA control unit 3 via the DMA contact / separation signal line 14 to W
In the AIT state, access to the main memory 4 is waited.

In FIG. 3, a CPU contact / separation signal line 13 is connected between the CPU 1 and the contact / separation arbitration unit 6, and a DMA control unit (D
2 shows a state in which a DMA contact / separation signal line 14 is connected between the MAC) 3 and the contact / separation arbitration unit 6. The signals on the CPU contact / separation signal line 13 and the DMA contact / separation signal line 14 both indicate a part of the signal for accessing the main memory 4 and the direction of the signal. FIG. 4 shows an example of a normal timing state of a signal for accessing the main memory 4 from the CPU 1 and the DMA control unit 3. For example, from CPU1, READ
(Read) signal or WRITE (write)
Outputs signals as required. When a READ or WRITE (R / W) signal is output, a CSMEM signal, which is a chip select signal to the memory, is output immediately. The contact / separation arbitration unit 6 sends a WAIT signal to the CPU 1 while the access to the main memory 4 is determined.
The transmission of data to the main memory 4 is waited. The width of the WAIT signal in the LOW state largely depends on the rising speed of the main memory 4.

FIG. 5 shows a case where the access from the DMA control unit 3 is prioritized when the CPU 1 and the access to the main memory 4 from the DMA control unit 3 are performed at the same time, the CPU 1 is in the WAIT state, FIG. 6 is a timing chart for waiting for access to the memory 4. DMAC: R / W, DMAC: C from the DMA control unit 3 side written in the lower part of FIG.
SMEM and signals such as addresses (not shown) are input to the main memory 4. During that time, the CPU 1 is put on WAIT. When the access from the DMA control unit 3 ends, the CPU: R / W, CPU: CSM
EM and signals such as addresses (not shown) are stored in the main memory 4.
Is input to Therefore, the CPU 1 and the DMA control unit 3 cannot proceed to the next access until the WAIT signal is released.

[0014]

As described above, according to the first aspect of the present invention,
When the first bus line and the second bus line are connected, it becomes possible for the CPU to access the storage means connected to the second bus line, and both bus lines are separated from each other. In such a case, independent operations can be performed in parallel, so that it is not necessary to secure a memory having a large capacity for storing data in both buses, and a data processing device capable of increasing the speed of the entire system can be provided. Claim 2
According to the invention of the first aspect, in addition to the invention of the data processing apparatus of the first aspect, even when data is transmitted and received by the DMA transfer,
Can access a device on the first bus line, so that a data processing device with improved system efficiency can be provided. According to the invention of claim 3, in addition to the invention of the data processing apparatus of claim 1 or claim 2, C
Since the PU or DMA control means can access the storage means without being conscious of the separation state between the first bus line and the second bus line, the operating range of the CPU and the DMA control means is expanded, An efficient data processing device for the entire system can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a main part of a data processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a close / separation arbitration unit of the data processing device shown in FIG. 1 in more detail;

FIG. 3 is an explanatory diagram showing a main part of a signal line connected to a contact / separation arbitration unit.

FIG. 4 is an explanatory diagram showing a normal timing example of a signal for accessing a main memory from a CPU and a DMA control unit.

FIG. 5 is an explanatory diagram showing an example of timing when access from the CPU and the DMA control unit to the main memory 4 is performed simultaneously.

[Explanation of symbols]

1 CPU, 2 system bus (first bus line), 3 DMA controller (DMA controller), 4
... Main memory (storage means), 5 ... I / O bus (second bus line), 6 ... Connection / separation arbitration unit (contact / separation arbitration means), 6a ... Connection / separation arbitration control unit , 6b: contact / separation execution unit, 7: image processing unit, 8: sub memory, 9
..ROM, 10 external interfaces, 11
..System arbitration bus, 11a... System bus control line, 11b.
..I / O arbitration bus, 12a ... I / O bus control line, 12b ... I / O connection / separation line, 13 ... CPU
Attachment / separation signal line, 14 ... DMA Attachment / separation signal line, 20 ...
Image processing device (data processing device), 21 external device

Claims (3)

[Claims] 1. A data processing device for transmitting and receiving data to and from an external device by DMA transfer, comprising: a first bus line connected to a CPU; and a DM bus for controlling DMA transfer.
A control means, storage means for storing data to be transmitted and received by DMA transfer, a second bus line connecting the DMA control means and the storage means, the first bus line and the second bus line And a connection / separation arbitration means for connecting or disconnecting the first bus line and the second bus line. 2. The data processing apparatus according to claim 1, wherein the connection / separation arbitration unit is connected to the first bus line and the second bus line while the image data is transmitted and received by the DMA transfer through the second bus line. A data processing device characterized in that it is separated from a bus line. 3. The data processing device according to claim 1, wherein an access from the CPU to the storage unit is performed by the CPU.
When the access to the storage means for writing the transmission / reception data by the DMA transfer is performed simultaneously, the connection / separation arbitration means sets the CPU or the DMA control means, to which the access is rejected, to the WAIT state. A data processing device characterized by the above-mentioned.