JPH039454A - Cpu multiplexing bus system - Google Patents

Abstract

PURPOSE:To prevent the generation of a pin neck without requiring an access space of large capacity by controlling the separation of multiplexing data and selecting a package to be accessed. CONSTITUTION:A CPU package 1 is provided with a bidirectional buffer 12 for a multiplexing data I/O port, a multiplexing bus control signal output port 13 and an address decoding part 21 and a package 2 to be accessed is provided with a bidirectional buffer 14 for a multiplexing data I/O port, a multiplexing bus control signal input port 15 and a selection part 19 for selecting the accessed package 2. In the accessed package 2, an accessed package selection signal is compared with a self-package signal by the selection part 19 and the buffer 14 forming the multi-plexing data I/O port is set up on the input side by the control part 16. Consequently, the number of interface signal lines can be reduced and the CPU access space of large capacity can be secured.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an improvement in a CPU multiplexed bus system, and in particular to a CPU multiplexed bus system.
The present invention relates to a CPU multiplexing bus method of bus multiplexing processing that is effective when there are many packages to be accessed for a U-mounted package.

(Prior Art) Conventionally, an address bar,
A first method of accessing the OPU using a control bus and a second method of having the address decoding section owned by the OPU mounting section and accessing it using chip select information and a data bus control bus are known.

(Problems to be Solved by the Invention) In the first method described above, in which the interface between the CPU-equipped package and the accessed package is accessed using an address bus, a data bus, and a control bus, there are a large number of buses. Therefore, there is a drawback that a bin neck occurs due to the overlap between the CPU mounting package and the accessed package.

2. The address decoding section is located in the CPU package, and the number of bus configuration signal lines such as the data bus and control bus is reduced using chip select information.
The disadvantage of this method is that it is necessary to secure a large amount of access space.

To summarize all of the above drawbacks, conventional interfaces have drawbacks such as requiring a large amount of access space or having a large number of buses, resulting in bin necks between packages.

An object of the present invention is to provide address decoding means, multiplexed data input/output port means, and multiplexed bus control signal output port means on the side of a CPU-mounted package, and to provide multiplexed data input/output port means on the accessed package side. By providing a multiplexed bus control signal input port means and controlling the separation of multiplexed data to select the package to be accessed, the above-mentioned drawbacks are eliminated, and the entire large capacity access space is not required and bin necks occur. It is designed to provide a total of 90 PU multiplexed path systems.

(Means for Solving the Problems) A CPU multiplexed bus system according to the present invention is configured to include an accessed package and a CPU mounting package.

In the above, the accessed package includes first multiplexed data input/output port means, multiplexed bus control signal input port means, control means, address latch means, and selection means. .

The first multiplexed data input/output port means is for reading address information and reading/writing data information.

The multiplexed bus control signal input port means is for reading multiplexed control information and multiplexed read/write information.

The control means is for separating multiplexed control information and multiplexed read/write information.

The address latch means is for latching address information obtained by one separation.

The selection means is for selecting over the multiplexed bus control signal input port means.

On the other hand, in the above configuration, the CPU-mounted package includes second multiplexed data input/output port means, multiplexed bus control signal output port means, and address decoding means.

The second multiplexed data input/output port means is for writing address information and for reading/writing data information.

The multiplexed bus control signal output port means is for writing multiplexed control information and multiplexed read/write information.

The address decoding means is for decoding the addresses of the multiplexed data input/output port means and the multiplexed bus control signal output port means.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the CPU multiplexed bus system according to the present invention.

FIG. 1 is a block diagram showing an embodiment of a CPU multiplexed bus system according to the present invention.

In FIG. 1, 1 is a CPU mounting package, and 2 is an accessed package. In the OPU-equipped package 1, 11 is an OPU, 12 is a bidirectional buffer, 13 is an output port), and 21 is a 7-dress decoder unit. In the accessed package 2, 14 is a bidirectional buffer, 15 is an input port, 16 is a control section, 17 and 18 are address latch sections, and 19 is a selection section.

The OPU package 1 has a data bus 110. In addition to the address bus 111 and the control bus 112, a bidirectional buffer 12 for multiplexed data input/output ports is connected to the control bus 112 and is related to the present invention. It is configured as an address decoder 211-V for the output port 13 of the multiplexed bus control signal and the output port 13.

The accessed package 2 includes a buffer 14 for multiplexed data input/output ports as a functional part related to the present invention.
．． Multi 31 [input capo of bus control signal] 15,
It is configured to include a multiplexed bus branching agent control section 16, an address latch section 17 for upper addresses, an address latch section 18 for lower addresses, and a selection section 19 for selecting an accessed package 2.

Next, the operation of the present invention will be explained.

When writing data to the OPU access space of the accessed package 2, the accessed package selection signal on the signal line 133, the multiplexed bus read signal on the signal line 130, and the multiplexed bus write signal 10PU on the signal line 131 are used.
Multiplexed bus control (1
write to output port 13 of. Next, after writing the lower address sequence information on the signal line 132 to the input port 15, the lower address information is written to the bidirectional buffer 12 forming the multiplexed data input/output port.

Next, turn off the multiple bus write signal on the signal line 131→
By changing from ON to OFF, a write pulse is generated from the trap, and the accessed package 2 is sent via the signal line 120.
Write lower address information to. Note that when a write pulse is generated, other data is held.

In the accessed package 2, the accessed package selection signal on the signal line 133 and the own package signal on the signal line 191 are compared by the accessed package signal selection unit 19.

As a result of the comparison, if the above information is the same, a package selection signal is output onto the signal line 190, and the multiplexed bus control signal input port 15'i is opened.

Therefore, the multiplexed bus read signal on signal line 130.150, the multiplexed bus write signal on signal line 131.151,
Furthermore, the lower address sequence information on the signal lines 132 and 152 is inputted to the multiplexed bus separation control unit 16 through red and white input ports 1s, respectively.

Based on the above information, the multiplexed bus separation control unit 16
outputs switching information onto the signal line 160 before a signal is input to the accessed package 2, and sets the bidirectional buffer 14 forming a multiplexed data input/output port at the input end. From this point on, lower address information is input onto the signal line 120. At this time, the control unit 16 controls the signal line 162'
A lower address latch lock is output to the lower address latch unit 18 via i, and lower address information is held.

The above operation is performed as one bus cycle.

Upper address information is the same as above a! The data is rewritten in the order of lower address information→upper address information→lower address sequence information→upper 7 address sequence information by the bus cycle, and when the above bus cycle operates, the upper address information is held.

The write data is also changed in the order of upper address information → stored data → upper address sequence information → data sequence information, and when the above bus cycle operates in the same manner, a write signal is sent from the control unit 16 for multiplexed bus separation onto the signal line 164. Output. This makes it possible to write data to the gold wave access package 2.

By the above bus cycle operation, write data and data write signals are output after the lower/upper addresses are determined, so by using all these addresses, data, data, and write signals, normal OPU access can be achieved. becomes possible.

Next, when data is output from the OPU access port of the accessed package 2, the lower address information and upper address information are determined as lower/upper addresses by operating the same bus cycle as when writing data. Ru.

Next, the multiplexed bus write information is turned off in the read data, and the data sequence information is written.

Next, by writing the multiplexed bus read signal OFF→ON→0FFy to the output port 13 of the multiplexed bus control signal, the signal line 16 is transferred from the control unit 15 for multiplexed bus separation.
A direction control signal is output on 0, which switches the bidirectional buffer 14 forming the data input/output port to the output direction. As a result, in the accessed package 2, the data at the designated address is output as a multiplexed data bus signal onto the signal line 120 via the bidirectional buffer 14 forming the multiplexed data input/output port, and the multiplexed data input/output port is CP via the bidirectional buffer 12 forming
It is input into U loading package l.

Data can be read from the accessed package 2 by reading the contents of the bidirectional buffer 12 forming the multiplexed data input/output port after the multiplexed bus read signal is turned off.

(Effects of the Invention) As explained above, the present invention can completely reduce the number of interface signal lines between a CPU-equipped package and a large number of accessed packages by multiplexing address buses and data buses. , even if the interface signal lines are reduced, large-capacity OPU
This has the effect of ensuring access space.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the OPU bus system according to the present invention. 1...CPU mounting package 2...Accessed package 12.14-...Bidirectional buffer 13...Output port 15...Input port 16.
...Control section 17.18... Address latch section 19... Selection section 21... Address decoder section 1
10-112, 120, 140...Bus 130-13
3.150~152,160~164°170.180
, 190, 191, 210, 211... signal line

Claims (1)

[Claims] A CPU multiplexed bus system comprising an accessed package and a CPU mounting package, wherein the accessed package has a first multiplexed data input for reading address information and reading/writing data information. output port means, multiplexed bus control signal input port means for reading multiplexed control information and multiplexed read/write information, and control means for separating said multiplexed control information and multiplexed read/write information. , address latch means for latching the address information obtained by the separation, and selection means for selecting the multiplexed bus control signal input port means; a second multiplexed data input/output port means for writing information and performing reading/writing of said data information; and a multiplexing bus control for writing said multiplexed control information and said multiplexed read/write information. C, characterized in that it is configured to include signal output port means, and address decoding means for decoding the addresses of the multiplexed data input/output port means and the multiplexed bus control signal output port means.
PU multiplexed bus system.